Intel 253666-024US Manuale Utente

Intel® 64 and IA-32 ArchitecturesSoftware Developer’s ManualVolume 2A:Instruction Set Reference, A-MNOTE: The Intel 64 and IA-32 Architectures Softwar

CONTENTSxVol. 2APAGEPAVGB/PAVGW—Average Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61PCMPEQB/PCMPEQ

3-54 Vol. 2A AND—Logical ANDINSTRUCTION SET REFERENCE, A-MDescriptionPerforms a bitwise AND operation on the destination (first) and source (second) o

Vol. 2A 3-55INSTRUCTION SET REFERENCE, A-MAND—Logical AND#UD If the LOCK prefix is used but the destination is not a memory operand.Virtual-8086 Mode

3-56 Vol. 2A ANDPD—Bitwise Logical AND of Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MANDPD—Bitwise Logical AND of Pack

Vol. 2A 3-57INSTRUCTION SET REFERENCE, A-MANDPD—Bitwise Logical AND of Packed Double-Precision Floating-Point ValuesReal-Address Mode Exceptions#GP(0)

3-58 Vol. 2A ANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MANDPS—Bitwise Logical AND of Pack

Vol. 2A 3-59INSTRUCTION SET REFERENCE, A-MANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point ValuesReal-Address Mode Exceptions#GP(0)

3-60 Vol. 2A ANDNPD—Bitwise Logical AND NOT of Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MANDNPD—Bitwise Logical AND N

Vol. 2A 3-61INSTRUCTION SET REFERENCE, A-MANDNPD—Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values#UD If CR0.EM[bit 2] = 1.If

3-62 Vol. 2A ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MANDNPS—Bitwise Logical AND N

Vol. 2A 3-63INSTRUCTION SET REFERENCE, A-MANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-Point ValuesReal-Address Mode Exceptions#

Vol. 2A xiCONTENTSPAGEPUSH—Push Word, Doubleword or Quadword Onto the Stack . . . . . . . . . . . . . . . . . . . 4-217PUSHA/PUSHAD—Push All General-P

3-64 Vol. 2A ARPL—Adjust RPL Field of Segment SelectorINSTRUCTION SET REFERENCE, A-MARPL—Adjust RPL Field of Segment SelectorDescriptionCompares the R

Vol. 2A 3-65INSTRUCTION SET REFERENCE, A-MARPL—Adjust RPL Field of Segment SelectorELSEZF ← 0;FI;FI;Flags AffectedThe ZF flag is set to 1 if the RPL f

3-66 Vol. 2A BOUND—Check Array Index Against BoundsINSTRUCTION SET REFERENCE, A-MBOUND—Check Array Index Against BoundsDescriptionBOUND determines if

Vol. 2A 3-67INSTRUCTION SET REFERENCE, A-MBOUND—Check Array Index Against BoundsFlags AffectedNone.Protected Mode Exceptions#BR If the bounds test fai

3-68 Vol. 2A BOUND—Check Array Index Against BoundsINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-

Vol. 2A 3-69INSTRUCTION SET REFERENCE, A-MBSF—Bit Scan ForwardBSF—Bit Scan ForwardDescriptionSearches the source operand (second operand) for the leas

3-70 Vol. 2A BSF—Bit Scan ForwardINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0) If a memory operand effective address is outside the CS

Vol. 2A 3-71INSTRUCTION SET REFERENCE, A-MBSR—Bit Scan ReverseBSR—Bit Scan ReverseDescriptionSearches the source operand (second operand) for the most

3-72 Vol. 2A BSR—Bit Scan ReverseINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0) If a memory operand effective address is outside the CS

Vol. 2A 3-73INSTRUCTION SET REFERENCE, A-MBSWAP—Byte SwapBSWAP—Byte SwapDescriptionReverses the byte order of a 32-bit or 64-bit (destination) registe

CONTENTSxiiVol. 2APAGESYSCALL—Fast System Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-74 Vol. 2A BSWAP—Byte SwapINSTRUCTION SET REFERENCE, A-MDEST[15:8] ← TEMP[23:16];DEST[23:16] ← TEMP[15:8];DEST[31:24] ← TEMP[7:0];FI;Flags AffectedN

Vol. 2A 3-75INSTRUCTION SET REFERENCE, A-MBT—Bit TestBT—Bit TestDescriptionSelects the bit in a bit string (specified with the first operand, called t

3-76 Vol. 2A BT—Bit TestINSTRUCTION SET REFERENCE, A-MOr, it may access 2 bytes starting from the memory address for a 16-bit operand, using this rela

Vol. 2A 3-77INSTRUCTION SET REFERENCE, A-MBT—Bit TestVirtual-8086 Mode Exceptions#GP(0) If a memory operand effective address is outside the CS, DS, E

3-78 Vol. 2A BTC—Bit Test and ComplementINSTRUCTION SET REFERENCE, A-MBTC—Bit Test and ComplementDescriptionSelects the bit in a bit string (specified

Vol. 2A 3-79INSTRUCTION SET REFERENCE, A-MBTC—Bit Test and Complementprefix in the form of REX.W promotes operation to 64 bits. See the summary chart

3-80 Vol. 2A BTC—Bit Test and ComplementINSTRUCTION SET REFERENCE, A-M#AC(0) If alignment checking is enabled and an unaligned memory reference is mad

Vol. 2A 3-81INSTRUCTION SET REFERENCE, A-MBTR—Bit Test and ResetBTR—Bit Test and ResetDESCRIPTIONSelects the bit in a bit string (specified with the f

3-82 Vol. 2A BTR—Bit Test and ResetINSTRUCTION SET REFERENCE, A-Mprefix in the form of REX.W promotes operation to 64 bits. See the summary chart at t

Vol. 2A 3-83INSTRUCTION SET REFERENCE, A-MBTR—Bit Test and Reset#AC(0) If alignment checking is enabled and an unaligned memory reference is made.#UD

Vol. 2A xiiiCONTENTSPAGECHAPTER 6SAFER MODE EXTENSIONS REFERENCE6.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-84 Vol. 2A BTS—Bit Test and SetINSTRUCTION SET REFERENCE, A-MBTS—Bit Test and SetDescriptionSelects the bit in a bit string (specified with the firs

Vol. 2A 3-85INSTRUCTION SET REFERENCE, A-MBTS—Bit Test and Setprefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the

3-86 Vol. 2A BTS—Bit Test and SetINSTRUCTION SET REFERENCE, A-M#AC(0) If alignment checking is enabled and an unaligned memory reference is made.#UD

Vol. 2A 3-87INSTRUCTION SET REFERENCE, A-MCALL—Call ProcedureCALL—Call ProcedureDescriptionSaves procedure linking information on the stack and branch

3-88 Vol. 2A CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-Mthe first instruction in the called procedure. The operand can be an immediate value, a

Vol. 2A 3-89INSTRUCTION SET REFERENCE, A-MCALL—Call Procedureor 64 bits). In 64-bit mode the target operand will always be 64-bits because the operand

3-90 Vol. 2A CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-Msegment selector for the new code segment and the new instruction pointer (offset) from

Vol. 2A 3-91INSTRUCTION SET REFERENCE, A-MCALL—Call ProcedureFar Calls in Compatibility Mode. When the processor is operating in compatibility mode, t

3-92 Vol. 2A CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-Mpushes the segment selector and stack pointer for the calling procedure’s stack and the

Vol. 2A 3-93INSTRUCTION SET REFERENCE, A-MCALL—Call ProcedureNote that when using a call gate to perform a far call to a segment at the same priv-ileg

CONTENTSxivVol. 2APAGEA.5.2.3 Escape Opcodes with DA as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25A

3-94 Vol. 2A CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-MTHENtempRIP ← DEST; (* DEST is r/m64 *)IF stack not large enough for a 8-byte return add

Vol. 2A 3-95INSTRUCTION SET REFERENCE, A-MCALL—Call ProcedurePush(IP);CS ← DEST[31:16]; (* DEST is ptr16:16 or [m16:16] *)EIP ← DEST[15:0]; (* DEST is

3-96 Vol. 2A CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-MtempEIP ← tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *)IF (EFER.LMA = 0 or target

Vol. 2A 3-97INSTRUCTION SET REFERENCE, A-MCALL—Call ProceduretempEIP ← DEST(Offset);IF OperandSize = 16THEN tempEIP ← tempEIP AND 0000FFFFH; FI; (* Cl

3-98 Vol. 2A CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-MTHEN #GP(code segment selector); FI;Read code segment descriptor;IF code-segment segment

Vol. 2A 3-99INSTRUCTION SET REFERENCE, A-MCALL—Call Procedureor stack segment DPL ≠ DPL of code segment or stack segment is not awritable data segment

3-100 Vol. 2A CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-M(* Segment descriptor information also loaded *)Push(oldSS:oldESP); (* From calling pro

Vol. 2A 3-101INSTRUCTION SET REFERENCE, A-MCALL—Call ProcedureTHEN #GP(task gate selector); FI;IF task gate not present THEN #NP(task gate selector);

3-102 Vol. 2A CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-M#GP(selector) If a code segment or gate or TSS selector index is outside descriptor tab

Vol. 2A 3-103INSTRUCTION SET REFERENCE, A-MCALL—Call ProcedureIf the RPL of the new stack segment selector in the TSS is not equal to the DPL of the c

Vol. 2A xvCONTENTSPAGEFIGURESFigure 1-1. Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-104 Vol. 2A CALL—Call ProcedureINSTRUCTION SET REFERENCE, A-MIf code segment or 64-bit call gate overlaps non-canonical space. If the segment descri

Vol. 2A 3-105INSTRUCTION SET REFERENCE, A-MCBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Double-word to QuadwordCBW/CWDE/CDQE—

3-106 Vol. 2A CLC—Clear Carry FlagINSTRUCTION SET REFERENCE, A-MCLC—Clear Carry FlagDescriptionClears the CF flag in the EFLAGS register. Operation is

Vol. 2A 3-107INSTRUCTION SET REFERENCE, A-MCLD—Clear Direction FlagCLD—Clear Direction FlagDescriptionClears the DF flag in the EFLAGS register. When

3-108 Vol. 2A CLFLUSH—Flush Cache LineINSTRUCTION SET REFERENCE, A-MCLFLUSH—Flush Cache LineDescriptionInvalidates the cache line that contains the li

Vol. 2A 3-109INSTRUCTION SET REFERENCE, A-MCLFLUSH—Flush Cache LineOperationFlush_Cache_Line(SRC);Intel C/C++ Compiler Intrinsic EquivalentsCLFLUSH vo

3-110 Vol. 2A CLI — Clear Interrupt FlagINSTRUCTION SET REFERENCE, A-MCLI — Clear Interrupt FlagDescriptionIf protected-mode virtual interrupts are no

Vol. 2A 3-111INSTRUCTION SET REFERENCE, A-MCLI — Clear Interrupt FlagTHENIF IOPL ← CPLTHENIF ← 0; (* Reset Interrupt Flag *)ELSEIF ((IOPL < CPL) an

3-112 Vol. 2A CLI — Clear Interrupt FlagINSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode Exceptions#GP(0) If the CPL is greater (has less privilege) t

Vol. 2A 3-113INSTRUCTION SET REFERENCE, A-MCLTS—Clear Task-Switched Flag in CR0CLTS—Clear Task-Switched Flag in CR0DescriptionClears the task-switched

CONTENTSxviVol. 2APAGETABLESTable 2-1. 16-Bit Addressing Forms with the ModR/M Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6T

3-114 Vol. 2A CLTS—Clear Task-Switched Flag in CR0INSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-B

Vol. 2A 3-115INSTRUCTION SET REFERENCE, A-MCMC—Complement Carry FlagCMC—Complement Carry FlagDescriptionComplements the CF flag in the EFLAGS register

3-116 Vol. 2A CMOVcc—Conditional MoveINSTRUCTION SET REFERENCE, A-MCMOVcc—Conditional MoveOpcode Instruction 64-Bit ModeCompat/Leg ModeDescription0F 4

Vol. 2A 3-117INSTRUCTION SET REFERENCE, A-MCMOVcc—Conditional MoveOpcode Instruction 64-Bit ModeCompat/Leg ModeDescription0F 4D /r CMOVGE r32, r/m32 V

3-118 Vol. 2A CMOVcc—Conditional MoveINSTRUCTION SET REFERENCE, A-MOpcode Instruction 64-Bit ModeCompat/Leg ModeDescription0F 43 /r CMOVNC r16, r/m16

Vol. 2A 3-119INSTRUCTION SET REFERENCE, A-MCMOVcc—Conditional MoveOpcode Instruction 64-Bit ModeCompat/Leg ModeDescriptionREX.W + 0F 4B /r CMOVNP r64,

3-120 Vol. 2A CMOVcc—Conditional MoveINSTRUCTION SET REFERENCE, A-MDescriptionThe CMOVcc instructions check the state of one or more of the status fla

Vol. 2A 3-121INSTRUCTION SET REFERENCE, A-MCMOVcc—Conditional MoveDEST ← temp;FI;FI;Flags AffectedNone.Protected Mode Exceptions#GP(0) If a memory ope

3-122 Vol. 2A CMOVcc—Conditional MoveINSTRUCTION SET REFERENCE, A-M64-Bit Mode Exceptions#SS(0) If a memory address referencing the SS segment is in a

Vol. 2A 3-123INSTRUCTION SET REFERENCE, A-MCMP—Compare Two OperandsCMP—Compare Two OperandsOpcode Instruction 64-Bit ModeCompat/Leg ModeDescription3C

Vol. 2A xviiCONTENTSPAGETable 3-38. FPTAN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-124 Vol. 2A CMP—Compare Two OperandsINSTRUCTION SET REFERENCE, A-MDescriptionCompares the first source operand with the second source operand and se

Vol. 2A 3-125INSTRUCTION SET REFERENCE, A-MCMP—Compare Two OperandsVirtual-8086 Mode Exceptions#GP(0) If a memory operand effective address is outside

3-126 Vol. 2A CMPPD—Compare Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MCMPPD—Compare Packed Double-Precision Floating-

Vol. 2A 3-127INSTRUCTION SET REFERENCE, A-MCMPPD—Compare Packed Double-Precision Floating-Point ValuesThe unordered relationship is true when at least

3-128 Vol. 2A CMPPD—Compare Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MThe greater-than relations that the processor d

Vol. 2A 3-129INSTRUCTION SET REFERENCE, A-MCMPPD—Compare Packed Double-Precision Floating-Point ValuesCMPPD for inequality __m128d _mm_cmpneq_pd(__m12

3-130 Vol. 2A CMPPD—Compare Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#UD If an unmasked SIMD floating-point excepti

Vol. 2A 3-131INSTRUCTION SET REFERENCE, A-MCMPPS—Compare Packed Single-Precision Floating-Point ValuesCMPPS—Compare Packed Single-Precision Floating-P

3-132 Vol. 2A CMPPS—Compare Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MThe greater-than relations not implemented by t

Vol. 2A 3-133INSTRUCTION SET REFERENCE, A-MCMPPS—Compare Packed Single-Precision Floating-Point ValuesTHEN DEST95:64] ← FFFFFFFFH;ELSE DEST[95:64] ← 0

CONTENTSxviiiVol. 2APAGETable A-1. Superscripts Utilized in Opcode Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-134 Vol. 2A CMPPS—Compare Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MIf CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK pr

Vol. 2A 3-135INSTRUCTION SET REFERENCE, A-MCMPPS—Compare Packed Single-Precision Floating-Point Values#UD If an unmasked SIMD floating-point exceptio

3-136 Vol. 2A CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsINSTRUCTION SET REFERENCE, A-MCMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsOp

Vol. 2A 3-137INSTRUCTION SET REFERENCE, A-MCMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsDescriptionCompares the byte, word, doubleword, or quad

3-138 Vol. 2A CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsINSTRUCTION SET REFERENCE, A-MRDI) registers are assumed by the processor to specify

Vol. 2A 3-139INSTRUCTION SET REFERENCE, A-MCMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands(R|E)DI ← (R|E)DI – 2; FI;ELSE IF (Doubleword compariso

3-140 Vol. 2A CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsINSTRUCTION SET REFERENCE, A-M(E)SI ← (E)SI – 4; (E)DI ← (E)DI – 4; FI;FI;FI;Flags A

Vol. 2A 3-141INSTRUCTION SET REFERENCE, A-MCMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands64-Bit Mode Exceptions#SS(0) If a memory address refere

3-142 Vol. 2A CMPSD—Compare Scalar Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MCMPSD—Compare Scalar Double-Precision Floating-

Vol. 2A 3-143INSTRUCTION SET REFERENCE, A-MCMPSD—Compare Scalar Double-Precision Floating-Point ValuesThe greater-than relations not implemented in th

Vol. 2A xixCONTENTSPAGETable B-23. Format and Encoding of SSE Cacheability & Memory Ordering Instructions. . . . . .B-67Table B-24. Encoding of Gr

3-144 Vol. 2A CMPSD—Compare Scalar Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MCMPSD for greater-than-or-equal__m128d _mm_cmpg

Vol. 2A 3-145INSTRUCTION SET REFERENCE, A-MCMPSD—Compare Scalar Double-Precision Floating-Point ValuesIf CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[b

3-146 Vol. 2A CMPSS—Compare Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MCMPSS—Compare Scalar Single-Precision Floating-

Vol. 2A 3-147INSTRUCTION SET REFERENCE, A-MCMPSS—Compare Scalar Single-Precision Floating-Point ValuesThe greater-than relations not implemented in th

3-148 Vol. 2A CMPSS—Compare Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MCMPSS for less-than __m128 _mm_cmplt_ss(__m128

Vol. 2A 3-149INSTRUCTION SET REFERENCE, A-MCMPSS—Compare Scalar Single-Precision Floating-Point Values#UD If an unmasked SIMD floating-point exceptio

3-150 Vol. 2A CMPXCHG—Compare and ExchangeINSTRUCTION SET REFERENCE, A-MCMPXCHG—Compare and ExchangeDescriptionCompares the value in the AL, AX, EAX,

Vol. 2A 3-151INSTRUCTION SET REFERENCE, A-MCMPXCHG—Compare and ExchangeIn 64-bit mode, the instruction’s default operation size is 32 bits. Use of the

3-152 Vol. 2A CMPXCHG—Compare and ExchangeINSTRUCTION SET REFERENCE, A-MReal-Address Mode Exceptions#GP If a memory operand effective address is outsi

Vol. 2A 3-153INSTRUCTION SET REFERENCE, A-MCMPXCHG8B/CMPXCHG16B—Compare and Exchange BytesCMPXCHG8B/CMPXCHG16B—Compare and Exchange BytesDescriptionCo

ii Vol. 2AINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE,EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY

CONTENTSxxVol. 2APAGE

3-154 Vol. 2A CMPXCHG8B/CMPXCHG16B—Compare and Exchange BytesINSTRUCTION SET REFERENCE, A-MOperationIF (64-Bit Mode and OperandSize = 64)THENIF (RDX:R

Vol. 2A 3-155INSTRUCTION SET REFERENCE, A-MCMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes#SS If a memory operand effective address is outside the SS

3-156 Vol. 2A COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and SetEFLAGSINSTRUCTION SET REFERENCE, A-MCOMISD—Compare Scalar Or

Vol. 2A 3-157INSTRUCTION SET REFERENCE, A-MCOMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGSint _mm_comile_sd (__m12

3-158 Vol. 2A COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and SetEFLAGSINSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode Except

Vol. 2A 3-159INSTRUCTION SET REFERENCE, A-MCOMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGSCOMISS—Compare Scalar Or

3-160 Vol. 2A COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-Mint _mm_comile_ss (__m1

Vol. 2A 3-161INSTRUCTION SET REFERENCE, A-MCOMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGSVirtual-8086 Mode Except

3-162 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MCPUID—CPU IdentificationDescriptionThe ID flag (bit 21) in the EFLAGS register ind

Vol. 2A 3-163INSTRUCTION SET REFERENCE, A-MCPUID—CPU IdentificationSee also: “Serializing Instructions” in Chapter 7, “Multiple-Processor Management,”

Vol. 2A 1-1CHAPTER 1ABOUT THIS MANUALThe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B: Instruction Set Reference

3-164 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MCPUID leaves > 3 < 80000000 are visible only when IA32_MISC_ENABLES.BOOT_NT4

Vol. 2A 3-165INSTRUCTION SET REFERENCE, A-MCPUID—CPU IdentificationMONITOR/MWAIT Leaf 5H EAX Bits 15-00: Smallest monitor-line size in bytes (default

3-166 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-M0AH EAX Bits 07 - 00: Version ID of architectural performance monitoringBits 15- 0

Vol. 2A 3-167INSTRUCTION SET REFERENCE, A-MCPUID—CPU IdentificationEDX Bits 10-0: ReservedBit 11: SYSCALL/SYSRET available (when in 64-bit mode)Bits 1

3-168 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MINPUT EAX = 0: Returns CPUID’s Highest Value for Basic Processor Information and t

Vol. 2A 3-169INSTRUCTION SET REFERENCE, A-MCPUID—CPU IdentificationIA32_BIOS_SIGN_ID Returns Microcode Update SignatureFor processors that support the

3-170 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MSee Table 3-14 for available processor type values. Stepping IDs are provided as n

Vol. 2A 3-171INSTRUCTION SET REFERENCE, A-MCPUID—CPU Identification(* Right justify and zero-extend 4-bit field. *)FI;(* Show Display_Family as HEX fi

3-172 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-M Figure 3-6. Feature Information Returned in the ECX RegisterOM16524bCNXT-ID — L1

Vol. 2A 3-173INSTRUCTION SET REFERENCE, A-MCPUID—CPU IdentificationTable 3-15. Feature Information Returned in the ECX Register Bit # Mnemonic Desc

1-2 Vol. 2AABOUT THIS MANUAL• Intel® Core™2 Duo processor• Intel® Core™2 Quad processor• Intel® Xeon® processor 3000, 3200 series• Intel® Xeon® proces

3-174 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-M21 - 22 Reserved Reserved23 POPCNT A value of 1 indicates that the processor suppo

Vol. 2A 3-175INSTRUCTION SET REFERENCE, A-MCPUID—CPU IdentificationTable 3-16. More on Feature Information Returned in the EDX RegisterBit # Mnemoni

3-176 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-M13 PGE PTE Global Bit. The global bit in page directory entries (PDEs) and page t

Vol. 2A 3-177INSTRUCTION SET REFERENCE, A-MCPUID—CPU IdentificationINPUT EAX = 2: Cache and TLB Information Returned in EAX, EBX, ECX, EDXWhen CPUID e

3-178 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MTable 3-17. Encoding of Cache and TLB Descriptors Descriptor Value Cache or TLB D

Vol. 2A 3-179INSTRUCTION SET REFERENCE, A-MCPUID—CPU Identification56H Data TLB0: 4 MByte pages, 4-way set associative, 16 entries57H Data TLB0: 4 KBy

3-180 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MExample 3-1. Example of Cache and TLB InterpretationThe first member of the famil

Vol. 2A 3-181INSTRUCTION SET REFERENCE, A-MCPUID—CPU Identificationquery maximum number of cores per physical package by executing CPUID with EAX=4 an

3-182 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MThis method (introduced with Pentium 4 processors) returns an ASCII brand identifi

Vol. 2A 3-183INSTRUCTION SET REFERENCE, A-MCPUID—CPU IdentificationTable 3-18 shows the brand string that is returned by the first processor in the Pe

Vol. 2A 1-3ABOUT THIS MANUALChapter 1 — About This Manual. Gives an overview of all five volumes of the Intel® 64 and IA-32 Architectures Software Dev

3-184 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MThe Processor Brand Index MethodThe brand index method (introduced with Pentium® I

Vol. 2A 3-185INSTRUCTION SET REFERENCE, A-MCPUID—CPU Identificationdo not support the brand identification feature. Starting with processor signature

3-186 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MIA-32 Architecture CompatibilityCPUID is not supported in early models of the Inte

Vol. 2A 3-187INSTRUCTION SET REFERENCE, A-MCPUID—CPU IdentificationBREAKEAX = 4H:EAX ← Deterministic Cache Parameters Leaf; (* See Table 3-12. *)EBX ←

3-188 Vol. 2A CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MEAX = 80000002H:EAX ← Processor Brand String; EBX ← Processor Brand String, contin

Vol. 2A 3-189INSTRUCTION SET REFERENCE, A-MCPUID—CPU IdentificationEAX ← Reserved; (* Information returned for highest basic information leaf. *)EBX ←

3-190 Vol. 2A CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MCVTDQ2PD—Conve

Vol. 2A 3-191INSTRUCTION SET REFERENCE, A-MCVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point ValuesIf CPUID.01H:ED

3-192 Vol. 2A CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MCVTDQ2PS—Conve

Vol. 2A 3-193INSTRUCTION SET REFERENCE, A-MCVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values#NM If CR0.TS[b

1-4 Vol. 2AABOUT THIS MANUAL1.3.1 Bit and Byte OrderIn illustrations of data structures in memory, smaller addresses appear toward the bottom of the

3-194 Vol. 2A CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#NM If CR0.TS[

Vol. 2A 3-195INSTRUCTION SET REFERENCE, A-MCVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Double-word IntegersCVTPD2DQ—Conve

3-196 Vol. 2A CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Double-word IntegersINSTRUCTION SET REFERENCE, A-MIf a memory o

Vol. 2A 3-197INSTRUCTION SET REFERENCE, A-MCVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Double-word Integers#GP(0) If the

3-198 Vol. 2A CVTPD2PI—Convert Packed Double-Precision Floating-Point Values to Packed Double-word IntegersINSTRUCTION SET REFERENCE, A-MCVTPD2PI—Conv

Vol. 2A 3-199INSTRUCTION SET REFERENCE, A-MCVTPD2PI—Convert Packed Double-Precision Floating-Point Values to Packed Double-word IntegersProtected Mode

3-200 Vol. 2A CVTPD2PI—Convert Packed Double-Precision Floating-Point Values to Packed Double-word IntegersINSTRUCTION SET REFERENCE, A-MCompatibility

Vol. 2A 3-201INSTRUCTION SET REFERENCE, A-MCVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Va

3-202 Vol. 2A CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE

Vol. 2A 3-203INSTRUCTION SET REFERENCE, A-MCVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Va

Vol. 2A 1-5ABOUT THIS MANUAL1.3.2 Reserved Bits and Software CompatibilityIn many register and memory layout descriptions, certain bits are marked as

3-204 Vol. 2A CVTPI2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MCVTPI2PD—Conve

Vol. 2A 3-205INSTRUCTION SET REFERENCE, A-MCVTPI2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point ValuesProtected Mode

3-206 Vol. 2A CVTPI2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#MF If there

Vol. 2A 3-207INSTRUCTION SET REFERENCE, A-MCVTPI2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point ValuesCVTPI2PS—Conver

3-208 Vol. 2A CVTPI2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#PF(fault-code

Vol. 2A 3-209INSTRUCTION SET REFERENCE, A-MCVTPI2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values64-Bit Mode Exc

3-210 Vol. 2A CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Double-word IntegersINSTRUCTION SET REFERENCE, A-MCVTPS2DQ—Conv

Vol. 2A 3-211INSTRUCTION SET REFERENCE, A-MCVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Double-word Integers#SS(0) For an

3-212 Vol. 2A CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Double-word IntegersINSTRUCTION SET REFERENCE, A-MIf memory ope

Vol. 2A 3-213INSTRUCTION SET REFERENCE, A-MCVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Va

1-6 Vol. 2AABOUT THIS MANUAL1.3.3 Instruction OperandsWhen instructions are represented symbolically, a subset of the IA-32 assembly language is used.

3-214 Vol. 2A CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE

Vol. 2A 3-215INSTRUCTION SET REFERENCE, A-MCVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Va

3-216 Vol. 2A CVTPS2PI—Convert Packed Single-Precision Floating-Point Values to Packed Double-word IntegersINSTRUCTION SET REFERENCE, A-MCVTPS2PI—Conv

Vol. 2A 3-217INSTRUCTION SET REFERENCE, A-MCVTPS2PI—Convert Packed Single-Precision Floating-Point Values to Packed Double-word IntegersProtected Mode

3-218 Vol. 2A CVTPS2PI—Convert Packed Single-Precision Floating-Point Values to Packed Double-word IntegersINSTRUCTION SET REFERENCE, A-MCompatibility

Vol. 2A 3-219INSTRUCTION SET REFERENCE, A-MCVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword IntegerCVTSD2SI—Convert Scalar

3-220 Vol. 2A CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword IntegerINSTRUCTION SET REFERENCE, A-MSIMD Floating-Point Exc

Vol. 2A 3-221INSTRUCTION SET REFERENCE, A-MCVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword IntegerCompatibility Mode Excep

3-222 Vol. 2A CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Preci-sion Floating-Point ValueINSTRUCTION SET REFERENCE,

Vol. 2A 3-223INSTRUCTION SET REFERENCE, A-MCVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Preci-sion Floating-Point Va

Vol. 2A 1-7ABOUT THIS MANUALFor example, a program can keep its code (instructions) and stack in separate segments. Code addresses would always refer

3-224 Vol. 2A CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Preci-sion Floating-Point ValueINSTRUCTION SET REFERENCE,

Vol. 2A 3-225INSTRUCTION SET REFERENCE, A-MCVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point ValueCVTSI2SD—Convert Doublew

3-226 Vol. 2A CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptio

Vol. 2A 3-227INSTRUCTION SET REFERENCE, A-MCVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value64-Bit Mode Exceptions#S

3-228 Vol. 2A CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MCVTSI2SS—Convert Double

Vol. 2A 3-229INSTRUCTION SET REFERENCE, A-MCVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point ValueSIMD Floating-Point Exce

3-230 Vol. 2A CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MCompatibility Mode Exce

Vol. 2A 3-231INSTRUCTION SET REFERENCE, A-MCVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Preci-sion Floating-Point Va

3-232 Vol. 2A CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Preci-sion Floating-Point ValueINSTRUCTION SET REFERENCE,

Vol. 2A 3-233INSTRUCTION SET REFERENCE, A-MCVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Preci-sion Floating-Point Va

1-8 Vol. 2AABOUT THIS MANUAL1.4 RELATED LITERATURELiterature related to Intel 64 and IA-32 processors is listed on-line at: http://developer.intel.com

3-234 Vol. 2A CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword IntegerINSTRUCTION SET REFERENCE, A-MCVTSS2SI—Convert Scalar

Vol. 2A 3-235INSTRUCTION SET REFERENCE, A-MCVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword IntegerSIMD Floating-Point Exce

3-236 Vol. 2A CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword IntegerINSTRUCTION SET REFERENCE, A-MCompatibility Mode Exce

Vol. 2A 3-237INSTRUCTION SET REFERENCE, A-MCVTTPD2PI—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Intege

3-238 Vol. 2A CVTTPD2PI—Convert with Truncation Packed Double-Precision Floating-Point Values toPacked Doubleword IntegersINSTRUCTION SET REFERENCE, A

Vol. 2A 3-239INSTRUCTION SET REFERENCE, A-MCVTTPD2PI—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Intege

3-240 Vol. 2A CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Valuesto Packed Doubleword IntegersINSTRUCTION SET REFERENCE, A

Vol. 2A 3-241INSTRUCTION SET REFERENCE, A-MCVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Intege

3-242 Vol. 2A CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Valuesto Packed Doubleword IntegersINSTRUCTION SET REFERENCE, A

Vol. 2A 3-243INSTRUCTION SET REFERENCE, A-MCVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Intege

Vol. 2A 1-9ABOUT THIS MANUALliterature types: applications notes, data sheets, manuals, papers, and specification updates. See also: • The data sheet

3-244 Vol. 2A CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values toPacked Doubleword IntegersINSTRUCTION SET REFERENCE, A

Vol. 2A 3-245INSTRUCTION SET REFERENCE, A-MCVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Intege

3-246 Vol. 2A CVTTPS2PI—Convert with Truncation Packed Single-Precision Floating-Point Values toPacked Doubleword IntegersINSTRUCTION SET REFERENCE, A

Vol. 2A 3-247INSTRUCTION SET REFERENCE, A-MCVTTPS2PI—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Intege

3-248 Vol. 2A CVTTPS2PI—Convert with Truncation Packed Single-Precision Floating-Point Values toPacked Doubleword IntegersINSTRUCTION SET REFERENCE, A

Vol. 2A 3-249INSTRUCTION SET REFERENCE, A-MCVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Doubleword Integer

3-250 Vol. 2A CVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point Value toSigned Doubleword IntegerINSTRUCTION SET REFERENCE, A-M

Vol. 2A 3-251INSTRUCTION SET REFERENCE, A-MCVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Doubleword Integer

3-252 Vol. 2A CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value toDoubleword IntegerINSTRUCTION SET REFERENCE, A-MCVTTSS2

Vol. 2A 3-253INSTRUCTION SET REFERENCE, A-MCVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword IntegerIntel C

Vol. 2A iiiCONTENTSPAGECHAPTER 1ABOUT THIS MANUAL1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-10 Vol. 2AABOUT THIS MANUAL• Intel 64 and IA-32 processor manuals (printed or PDF downloads):http://developer.intel.com/products/processor/manuals/i

3-254 Vol. 2A CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value toDoubleword IntegerINSTRUCTION SET REFERENCE, A-M#AC(0)

Vol. 2A 3-255INSTRUCTION SET REFERENCE, A-MCWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to QuadwordCWD/CDQ/CQO—Convert Word to Doubleword

3-256 Vol. 2A CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to QuadwordINSTRUCTION SET REFERENCE, A-MRDX ← SignExtend(RAX); FI;FI;Flags Af

Vol. 2A 3-257INSTRUCTION SET REFERENCE, A-MDAA—Decimal Adjust AL after AdditionDAA—Decimal Adjust AL after AdditionDescriptionAdjusts the sum of two p

3-258 Vol. 2A DAA—Decimal Adjust AL after AdditionINSTRUCTION SET REFERENCE, A-MExampleADD AL, BL Before: AL=79H BL=35H EFLAGS(OSZAPC)=XXXXXXAfter:

Vol. 2A 3-259INSTRUCTION SET REFERENCE, A-MDAS—Decimal Adjust AL after SubtractionDAS—Decimal Adjust AL after SubtractionDescriptionAdjusts the result

3-260 Vol. 2A DAS—Decimal Adjust AL after SubtractionINSTRUCTION SET REFERENCE, A-MExampleSUB AL, BL Before: AL = 35H, BL = 47H, EFLAGS(OSZAPC) = XX

Vol. 2A 3-261INSTRUCTION SET REFERENCE, A-MDEC—Decrement by 1DEC—Decrement by 1DescriptionSubtracts 1 from the destination operand, while preserving t

3-262 Vol. 2A DEC—Decrement by 1INSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0) If the destination operand is located in a non-writable

Vol. 2A 3-263INSTRUCTION SET REFERENCE, A-MDEC—Decrement by 1#AC(0) If alignment checking is enabled and an unaligned memory reference is made while t

Vol. 2A 2-1CHAPTER 2INSTRUCTION FORMATThis chapter describes the instruction format for all Intel 64 and IA-32 processors. The instruction format for

3-264 Vol. 2A DIV—Unsigned DivideINSTRUCTION SET REFERENCE, A-MDIV—Unsigned DivideDescriptionDivides unsigned the value in the AX, DX:AX, EDX:EAX, or

Vol. 2A 3-265INSTRUCTION SET REFERENCE, A-MDIV—Unsigned DivideOperationIF SRC = 0THEN #DE; FI; (* Divide Error *) IF OperandSize = 8 (* Word/Byte Oper

3-266 Vol. 2A DIV—Unsigned DivideINSTRUCTION SET REFERENCE, A-MELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *)THENtem

Vol. 2A 3-267INSTRUCTION SET REFERENCE, A-MDIV—Unsigned DivideVirtual-8086 Mode Exceptions#DE If the source operand (divisor) is 0.If the quotient is

3-268 Vol. 2A DIVPD—Divide Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MDIVPD—Divide Packed Double-Precision Floating-Po

Vol. 2A 3-269INSTRUCTION SET REFERENCE, A-MDIVPD—Divide Packed Double-Precision Floating-Point Values#XM If an unmasked SIMD floating-point exception

3-270 Vol. 2A DIVPD—Divide Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#XM If an unmasked SIMD floating-point exceptio

Vol. 2A 3-271INSTRUCTION SET REFERENCE, A-MDIVPS—Divide Packed Single-Precision Floating-Point ValuesDIVPS—Divide Packed Single-Precision Floating-Poi

3-272 Vol. 2A DIVPS—Divide Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#NM If CR0.TS[bit 3] = 1. #XM If an unmasked SI

Vol. 2A 3-273INSTRUCTION SET REFERENCE, A-MDIVPS—Divide Packed Single-Precision Floating-Point Values#NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIM

2-2 Vol. 2AINSTRUCTION FORMAT• F2H—REPNE/REPNZ (used only with string instructions; when used with the escape opcode 0FH, this prefix is treated as a

3-274 Vol. 2A DIVSD—Divide Scalar Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MDIVSD—Divide Scalar Double-Precision Floating-Po

Vol. 2A 3-275INSTRUCTION SET REFERENCE, A-MDIVSD—Divide Scalar Double-Precision Floating-Point ValuesIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If

3-276 Vol. 2A DIVSD—Divide Scalar Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If

Vol. 2A 3-277INSTRUCTION SET REFERENCE, A-MDIVSS—Divide Scalar Single-Precision Floating-Point ValuesDIVSS—Divide Scalar Single-Precision Floating-Poi

3-278 Vol. 2A DIVSS—Divide Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If

Vol. 2A 3-279INSTRUCTION SET REFERENCE, A-MDIVSS—Divide Scalar Single-Precision Floating-Point ValuesIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If

3-280 Vol. 2A EMMS—Empty MMX Technology StateINSTRUCTION SET REFERENCE, A-MEMMS—Empty MMX Technology StateDescription Sets the values of all the tags

Vol. 2A 3-281INSTRUCTION SET REFERENCE, A-MEMMS—Empty MMX Technology StateVirtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibili

3-282 Vol. 2A ENTER—Make Stack Frame for Procedure ParametersINSTRUCTION SET REFERENCE, A-MENTER—Make Stack Frame for Procedure ParametersDescriptionC

Vol. 2A 3-283INSTRUCTION SET REFERENCE, A-MENTER—Make Stack Frame for Procedure ParametersOperationNestingLevel ← NestingLevel MOD 32IF 64-Bit Mode (S

Vol. 2A 2-3INSTRUCTION FORMATopcodes with Intel 64 or IA-32 instructions is reserved; such use may cause unpre-dictable behavior.The operand-size over

3-284 Vol. 2A ENTER—Make Stack Frame for Procedure ParametersINSTRUCTION SET REFERENCE, A-MFI;FI;OD;FI;IF 64-Bit Mode (StackSize = 64)THENPush(FrameTe

Vol. 2A 3-285INSTRUCTION SET REFERENCE, A-MENTER—Make Stack Frame for Procedure ParametersReal-Address Mode Exceptions#SS(0) If the new value of the S

3-286 Vol. 2A F2XM1—Compute 2x–1INSTRUCTION SET REFERENCE, A-MF2XM1—Compute 2x–1DescriptionComputes the exponential value of 2 to the power of the sou

Vol. 2A 3-287INSTRUCTION SET REFERENCE, A-MF2XM1—Compute 2x–1#U Result is too small for destination format.#P Value cannot be represented exactly in d

3-288 Vol. 2A FABS—Absolute ValueINSTRUCTION SET REFERENCE, A-MFABS—Absolute ValueDescriptionClears the sign bit of ST(0) to create the absolute value

Vol. 2A 3-289INSTRUCTION SET REFERENCE, A-MFABS—Absolute ValueReal-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode Excep

3-290 Vol. 2A FADD/FADDP/FIADD—AddINSTRUCTION SET REFERENCE, A-MFADD/FADDP/FIADD—AddDescriptionAdds the destination and source operands and stores the

Vol. 2A 3-291INSTRUCTION SET REFERENCE, A-MFADD/FADDP/FIADD—AddThe table on the following page shows the results obtained when adding various classes

3-292 Vol. 2A FADD/FADDP/FIADD—AddINSTRUCTION SET REFERENCE, A-MFPU Flags AffectedC1 Set to 0 if stack underflow occurred.Set if result was rounded up

Vol. 2A 3-293INSTRUCTION SET REFERENCE, A-MFADD/FADDP/FIADD—Add#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code) If a page fault occurs.#AC(0) If

2-4 Vol. 2AINSTRUCTION FORMAT2.1.3 ModR/M and SIB BytesMany instructions that refer to an operand in memory have an addressing-form spec-ifier byte (

3-294 Vol. 2A FBLD—Load Binary Coded DecimalINSTRUCTION SET REFERENCE, A-MFBLD—Load Binary Coded DecimalDescriptionConverts the BCD source operand int

Vol. 2A 3-295INSTRUCTION SET REFERENCE, A-MFBLD—Load Binary Coded DecimalReal-Address Mode Exceptions#GP If a memory operand effective address is outs

3-296 Vol. 2A FBSTP—Store BCD Integer and PopINSTRUCTION SET REFERENCE, A-MFBSTP—Store BCD Integer and PopDescriptionConverts the value in the ST(0) r

Vol. 2A 3-297INSTRUCTION SET REFERENCE, A-MFBSTP—Store BCD Integer and Popnation operand. If the invalid-operation exception is masked, the packed BCD

3-298 Vol. 2A FBSTP—Store BCD Integer and PopINSTRUCTION SET REFERENCE, A-M#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UD If the LOCK prefix is used.Virt

Vol. 2A 3-299INSTRUCTION SET REFERENCE, A-MFCHS—Change SignFCHS—Change SignDescriptionComplements the sign bit of ST(0). This operation changes a posi

3-300 Vol. 2A FCHS—Change SignINSTRUCTION SET REFERENCE, A-MReal-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode Excepti

Vol. 2A 3-301INSTRUCTION SET REFERENCE, A-MFCLEX/FNCLEX—Clear ExceptionsFCLEX/FNCLEX—Clear ExceptionsDescriptionClears the floating-point exception fl

3-302 Vol. 2A FCLEX/FNCLEX—Clear ExceptionsINSTRUCTION SET REFERENCE, A-MFPU Flags AffectedThe PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU

Vol. 2A 3-303INSTRUCTION SET REFERENCE, A-MFCMOVcc—Floating-Point Conditional MoveFCMOVcc—Floating-Point Conditional MoveDescriptionTests the status f

Vol. 2A 2-5INSTRUCTION FORMATlocation; the last eight (Mod = 11B) provide ways of specifying general-purpose, MMX technology and XMM registers. The Mo

3-304 Vol. 2A FCMOVcc—Floating-Point Conditional MoveINSTRUCTION SET REFERENCE, A-MOperationIF condition TRUETHEN ST(0) ← ST(i);FI;FPU Flags AffectedC

Vol. 2A 3-305INSTRUCTION SET REFERENCE, A-MFCMOVcc—Floating-Point Conditional MoveFCOM/FCOMP/FCOMPP—Compare Floating Point ValuesDescriptionCompares t

3-306 Vol. 2A FCMOVcc—Floating-Point Conditional MoveINSTRUCTION SET REFERENCE, A-MThe FCOMP instruction pops the register stack following the compari

Vol. 2A 3-307INSTRUCTION SET REFERENCE, A-MFCMOVcc—Floating-Point Conditional MoveFloating-Point Exceptions#IS Stack underflow occurred.#IA One or bot

3-308 Vol. 2A FCMOVcc—Floating-Point Conditional MoveINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.6

Vol. 2A 3-309INSTRUCTION SET REFERENCE, A-MFCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGSFCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compa

3-310 Vol. 2A FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-MIf the operation results in an in

Vol. 2A 3-311INSTRUCTION SET REFERENCE, A-MFCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGSZF, PF, CF ← 111;FI;FI;FI;IF Instr

3-312 Vol. 2A FCOS—CosineINSTRUCTION SET REFERENCE, A-MFCOS—CosineDescriptionComputes the cosine of the source operand in register ST(0) and stores th

Vol. 2A 3-313INSTRUCTION SET REFERENCE, A-MFCOS—CosineST(0) ← cosine(ST(0));ELSE (* Source operand is out-of-range *)C2 ← 1;FI;FPU Flags AffectedC1 Se

2-6 Vol. 2AINSTRUCTION FORMATNOTES:1. The default segment register is SS for the effective addresses containing a BP index, DS for othereffective addr

3-314 Vol. 2A FDECSTP—Decrement Stack-Top PointerINSTRUCTION SET REFERENCE, A-MFDECSTP—Decrement Stack-Top PointerDescriptionSubtracts one from the TO

Vol. 2A 3-315INSTRUCTION SET REFERENCE, A-MFDECSTP—Decrement Stack-Top PointerCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit

3-316 Vol. 2A FDIV/FDIVP/FIDIV—DivideINSTRUCTION SET REFERENCE, A-MFDIV/FDIVP/FIDIV—DivideDescriptionDivides the destination operand by the source ope

Vol. 2A 3-317INSTRUCTION SET REFERENCE, A-MFDIV/FDIVP/FIDIV—DivideIf an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if t

3-318 Vol. 2A FDIV/FDIVP/FIDIV—DivideINSTRUCTION SET REFERENCE, A-MIF Instruction = FDIVP THEN PopRegisterStack;FI;FPU Flags AffectedC1 Set to 0 if st

Vol. 2A 3-319INSTRUCTION SET REFERENCE, A-MFDIV/FDIVP/FIDIV—DivideVirtual-8086 Mode Exceptions#GP(0) If a memory operand effective address is outside

3-320 Vol. 2A FDIVR/FDIVRP/FIDIVR—Reverse DivideINSTRUCTION SET REFERENCE, A-MFDIVR/FDIVRP/FIDIVR—Reverse DivideDescriptionDivides the source operand

Vol. 2A 3-321INSTRUCTION SET REFERENCE, A-MFDIVR/FDIVRP/FIDIVR—Reverse DivideThe FIDIVR instructions convert an integer source operand to double exten

3-322 Vol. 2A FDIVR/FDIVRP/FIDIVR—Reverse DivideINSTRUCTION SET REFERENCE, A-MDEST ← SRC / DEST;FI;FI;IF Instruction = FDIVRP THEN PopRegisterStack;F

Vol. 2A 3-323INSTRUCTION SET REFERENCE, A-MFDIVR/FDIVRP/FIDIVR—Reverse Divide#SS If a memory operand effective address is outside the SS segment limit

Vol. 2A 2-7INSTRUCTION FORMATNOTES:1. The [--][--] nomenclature means a SIB follows the ModR/M byte.2. The disp32 nomenclature denotes a 32-bit displa

3-324 Vol. 2A FFREE—Free Floating-Point RegisterINSTRUCTION SET REFERENCE, A-MFFREE—Free Floating-Point RegisterDescriptionSets the tag in the FPU tag

Vol. 2A 3-325INSTRUCTION SET REFERENCE, A-MFICOM/FICOMP—Compare IntegerFICOM/FICOMP—Compare IntegerDescriptionCompares the value in ST(0) with an inte

3-326 Vol. 2A FICOM/FICOMP—Compare IntegerINSTRUCTION SET REFERENCE, A-MESAC;IF Instruction = FICOMP THEN PopRegisterStack; FI;FPU Flags AffectedC1 Se

Vol. 2A 3-327INSTRUCTION SET REFERENCE, A-MFICOM/FICOMP—Compare Integer#SS(0) If a memory operand effective address is outside the SS segment limit.#N

3-328 Vol. 2A FILD—Load IntegerINSTRUCTION SET REFERENCE, A-MFILD—Load IntegerDescriptionConverts the signed-integer source operand into double extend

Vol. 2A 3-329INSTRUCTION SET REFERENCE, A-MFILD—Load Integer#UD If the LOCK prefix is used.Real-Address Mode Exceptions#GP If a memory operand effect

3-330 Vol. 2A FINCSTP—Increment Stack-Top PointerINSTRUCTION SET REFERENCE, A-MFINCSTP—Increment Stack-Top PointerDescriptionAdds one to the TOP field

Vol. 2A 3-331INSTRUCTION SET REFERENCE, A-MFINCSTP—Increment Stack-Top PointerCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit

3-332 Vol. 2A FINIT/FNINIT—Initialize Floating-Point UnitINSTRUCTION SET REFERENCE, A-MFINIT/FNINIT—Initialize Floating-Point UnitDescriptionSets the

Vol. 2A 3-333INSTRUCTION SET REFERENCE, A-MFINIT/FNINIT—Initialize Floating-Point UnitOperationFPUControlWord ← 037FH;FPUStatusWord ← 0;FPUTagWord ← F

2-8 Vol. 2AINSTRUCTION FORMATof the table indicate the register used as the index (SIB byte bits 3, 4 and 5) and the scaling factor (determined by SIB

3-334 Vol. 2A FIST/FISTP—Store IntegerINSTRUCTION SET REFERENCE, A-MFIST/FISTP—Store IntegerDescriptionThe FIST instruction converts the value in the

Vol. 2A 3-335INSTRUCTION SET REFERENCE, A-MFIST/FISTP—Store IntegerIf the source value is a non-integral value, it is rounded to an integer value, acc

3-336 Vol. 2A FIST/FISTP—Store IntegerINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0) If the destination is located in a non-writable se

Vol. 2A 3-337INSTRUCTION SET REFERENCE, A-MFIST/FISTP—Store Integer#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MF If there is a pending x87 FPU exception

3-338 Vol. 2A FISTTP—Store Integer with TruncationINSTRUCTION SET REFERENCE, A-MFISTTP—Store Integer with TruncationDescriptionFISTTP converts the val

Vol. 2A 3-339INSTRUCTION SET REFERENCE, A-MFISTTP—Store Integer with TruncationNumeric ExceptionsInvalid, Stack Invalid (stack underflow), Precision.P

3-340 Vol. 2A FISTTP—Store Integer with TruncationINSTRUCTION SET REFERENCE, A-M64-Bit Mode Exceptions#SS(0) If a memory address referencing the SS se

Vol. 2A 3-341INSTRUCTION SET REFERENCE, A-MFLD—Load Floating Point ValueFLD—Load Floating Point ValueDescriptionPushes the source operand onto the FPU

3-342 Vol. 2A FLD—Load Floating Point ValueINSTRUCTION SET REFERENCE, A-M#IA Source operand is an SNaN. Does not occur if the source operand is in dou

Vol. 2A 3-343INSTRUCTION SET REFERENCE, A-MFLD—Load Floating Point ValueCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode

Vol. 2A 2-9INSTRUCTION FORMAT2.2 IA-32E MODEIA-32e mode has two sub-modes. These are: • Compatibility Mode. Enables a 64-bit operating system to run m

3-344 Vol. 2A FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load ConstantINSTRUCTION SET REFERENCE, A-MFLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load

Vol. 2A 3-345INSTRUCTION SET REFERENCE, A-MFLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load ConstantFloating-Point Exceptions#IS Stack overflow occurr

3-346 Vol. 2A FLDCW—Load x87 FPU Control WordINSTRUCTION SET REFERENCE, A-MFLDCW—Load x87 FPU Control WordDescriptionLoads the 16-bit source operand i

Vol. 2A 3-347INSTRUCTION SET REFERENCE, A-MFLDCW—Load x87 FPU Control Word#AC(0) If alignment checking is enabled and an unaligned memory reference is

3-348 Vol. 2A FLDENV—Load x87 FPU EnvironmentINSTRUCTION SET REFERENCE, A-MFLDENV—Load x87 FPU EnvironmentDescriptionLoads the complete x87 FPU operat

Vol. 2A 3-349INSTRUCTION SET REFERENCE, A-MFLDENV—Load x87 FPU EnvironmentFPU Flags AffectedThe C0, C1, C2, C3 flags are loaded.Floating-Point Excepti

3-350 Vol. 2A FLDENV—Load x87 FPU EnvironmentINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mo

Vol. 2A 3-351INSTRUCTION SET REFERENCE, A-MFMUL/FMULP/FIMUL—MultiplyFMUL/FMULP/FIMUL—MultiplyDescriptionMultiplies the destination and source operands

3-352 Vol. 2A FMUL/FMULP/FIMUL—MultiplyINSTRUCTION SET REFERENCE, A-MThe FIMUL instructions convert an integer source operand to double extended-preci

Vol. 2A 3-353INSTRUCTION SET REFERENCE, A-MFMUL/FMULP/FIMUL—MultiplyFPU Flags AffectedC1 Set to 0 if stack underflow occurred.Set if result was rounde

CONTENTSivVol. 2APAGE3.1.1.5 Description Column in the Instruction Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . 3-73.1.1.6 Descri

2-10 Vol. 2AINSTRUCTION FORMAT2.2.1.1 EncodingIntel 64 and IA-32 instruction formats specify up to three registers by using 3-bit fields in the enco

3-354 Vol. 2A FMUL/FMULP/FIMUL—MultiplyINSTRUCTION SET REFERENCE, A-M#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code) If a page fault occurs.#AC

Vol. 2A 3-355INSTRUCTION SET REFERENCE, A-MFNOP—No OperationFNOP—No OperationDescriptionPerforms no FPU operation. This instruction takes up space in

3-356 Vol. 2A FPATAN—Partial ArctangentINSTRUCTION SET REFERENCE, A-MFPATAN—Partial ArctangentDescriptionComputes the arctangent of the source operand

Vol. 2A 3-357INSTRUCTION SET REFERENCE, A-MFPATAN—Partial ArctangentThere is no restriction on the range of source operands that FPATAN can accept.Thi

3-358 Vol. 2A FPATAN—Partial ArctangentINSTRUCTION SET REFERENCE, A-MFloating-Point Exceptions#IS Stack underflow occurred.#IA Source operand is an SN

Vol. 2A 3-359INSTRUCTION SET REFERENCE, A-MFPREM—Partial RemainderFPREM—Partial RemainderDescriptionComputes the remainder obtained from dividing the

3-360 Vol. 2A FPREM—Partial RemainderINSTRUCTION SET REFERENCE, A-MThe FPREM instruction does not compute the remainder specified in IEEE Std 754. The

Vol. 2A 3-361INSTRUCTION SET REFERENCE, A-MFPREM—Partial RemainderFPU Flags AffectedC0 Set to bit 2 (Q2) of the quotient.C1 Set to 0 if stack underflo

3-362 Vol. 2A FPREM1—Partial RemainderINSTRUCTION SET REFERENCE, A-MFPREM1—Partial RemainderDescriptionComputes the IEEE remainder obtained from divid

Vol. 2A 3-363INSTRUCTION SET REFERENCE, A-MFPREM1—Partial RemainderThe FPREM1 instruction computes the remainder specified in IEEE Standard 754. This

Vol. 2A 2-11INSTRUCTION FORMATTable 2-4. REX Prefix Fields [BITS: 0100WRXB]Field Name Bit Position Definition- 7:4 0100W 3 0 = Operand size determine

3-364 Vol. 2A FPREM1—Partial RemainderINSTRUCTION SET REFERENCE, A-MC2 Set to 0 if reduction complete; set to 1 if incomplete.C3 Set to bit 1 (Q1) of

Vol. 2A 3-365INSTRUCTION SET REFERENCE, A-MFPTAN—Partial TangentFPTAN—Partial TangentDescriptionComputes the tangent of the source operand in register

3-366 Vol. 2A FPTAN—Partial TangentINSTRUCTION SET REFERENCE, A-MThis instruction’s operation is the same in non-64-bit modes and 64-bit mode.Operatio

Vol. 2A 3-367INSTRUCTION SET REFERENCE, A-MFPTAN—Partial TangentCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptio

3-368 Vol. 2A FRNDINT—Round to IntegerINSTRUCTION SET REFERENCE, A-MFRNDINT—Round to IntegerDescriptionRounds the source value in the ST(0) register t

Vol. 2A 3-369INSTRUCTION SET REFERENCE, A-MFRNDINT—Round to IntegerCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Excep

3-370 Vol. 2A FRSTOR—Restore x87 FPU StateINSTRUCTION SET REFERENCE, A-MFRSTOR—Restore x87 FPU StateDescriptionLoads the FPU state (operating environm

Vol. 2A 3-371INSTRUCTION SET REFERENCE, A-MFRSTOR—Restore x87 FPU StateST(7) ← SRC[ST(7)];FPU Flags AffectedThe C0, C1, C2, C3 flags are loaded.Floati

3-372 Vol. 2A FRSTOR—Restore x87 FPU StateINSTRUCTION SET REFERENCE, A-M#AC(0) If alignment checking is enabled and an unaligned memory reference is m

Vol. 2A 3-373INSTRUCTION SET REFERENCE, A-MFSAVE/FNSAVE—Store x87 FPU StateFSAVE/FNSAVE—Store x87 FPU StateDescriptionStores the current FPU state (op

2-12 Vol. 2AINSTRUCTION FORMATIn the IA-32 architecture, byte registers (AH, AL, BH, BL, CH, CL, DH, and DL) are encoded in the ModR/M byte’s reg fiel

3-374 Vol. 2A FSAVE/FNSAVE—Store x87 FPU StateINSTRUCTION SET REFERENCE, A-Minstructions separately. If an exception is generated for either of these

Vol. 2A 3-375INSTRUCTION SET REFERENCE, A-MFSAVE/FNSAVE—Store x87 FPU StateFPU Flags AffectedThe C0, C1, C2, and C3 flags are saved and then cleared.F

3-376 Vol. 2A FSAVE/FNSAVE—Store x87 FPU StateINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit M

Vol. 2A 3-377INSTRUCTION SET REFERENCE, A-MFSCALE—ScaleFSCALE—ScaleDescriptionTruncates the value in the source operand (toward 0) to an integral valu

3-378 Vol. 2A FSCALE—ScaleINSTRUCTION SET REFERENCE, A-Mbefore the FXTRACT operation was performed. The FSTP ST(1) instruction overwrites the exponent

Vol. 2A 3-379INSTRUCTION SET REFERENCE, A-MFSIN—SineFSIN—SineDescriptionComputes the sine of the source operand in register ST(0) and stores the resul

3-380 Vol. 2A FSIN—SineINSTRUCTION SET REFERENCE, A-MST(0) ← sin(ST(0));ELSE (* Source operand out of range *)C2 ← 1;FI;FPU Flags AffectedC1 Set to 0

Vol. 2A 3-381INSTRUCTION SET REFERENCE, A-MFSINCOS—Sine and CosineFSINCOS—Sine and CosineDescriptionComputes both the sine and the cosine of the sourc

3-382 Vol. 2A FSINCOS—Sine and CosineINSTRUCTION SET REFERENCE, A-MOperationIF ST(0) < 263THENC2 ← 0;TEMP ← cosine(ST(0));ST(0) ← sine(ST(0));TOP ←

Vol. 2A 3-383INSTRUCTION SET REFERENCE, A-MFSINCOS—Sine and CosineCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Except

Vol. 2A 2-13INSTRUCTION FORMAT2.2.1.3 Displacement Addressing in 64-bit mode uses existing 32-bit ModR/M and SIB encodings. The ModR/M and SIB displ

3-384 Vol. 2A FSQRT—Square RootINSTRUCTION SET REFERENCE, A-MFSQRT—Square RootDescriptionComputes the square root of the source value in the ST(0) reg

Vol. 2A 3-385INSTRUCTION SET REFERENCE, A-MFSQRT—Square RootSource operand is a negative value (except for −0).#D Source operand is a denormal value.#

3-386 Vol. 2A FST/FSTP—Store Floating Point ValueINSTRUCTION SET REFERENCE, A-MFST/FSTP—Store Floating Point ValueDescriptionThe FST instruction copie

Vol. 2A 3-387INSTRUCTION SET REFERENCE, A-MFST/FSTP—Store Floating Point ValueIf the destination operand is a non-empty register, the invalid-operatio

3-388 Vol. 2A FST/FSTP—Store Floating Point ValueINSTRUCTION SET REFERENCE, A-MReal-Address Mode Exceptions#GP If a memory operand effective address i

Vol. 2A 3-389INSTRUCTION SET REFERENCE, A-MFSTCW/FNSTCW—Store x87 FPU Control WordFSTCW/FNSTCW—Store x87 FPU Control WordDescriptionStores the current

3-390 Vol. 2A FSTCW/FNSTCW—Store x87 FPU Control WordINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0) If the destination is located in a

Vol. 2A 3-391INSTRUCTION SET REFERENCE, A-MFSTCW/FNSTCW—Store x87 FPU Control Word#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MF If there is a pending x8

3-392 Vol. 2A FSTENV/FNSTENV—Store x87 FPU EnvironmentINSTRUCTION SET REFERENCE, A-MFSTENV/FNSTENV—Store x87 FPU EnvironmentDescriptionSaves the curre

Vol. 2A 3-393INSTRUCTION SET REFERENCE, A-MFSTENV/FNSTENV—Store x87 FPU EnvironmentIA-32 Architecture CompatibilityWhen operating a Pentium or Intel48

2-14 Vol. 2AINSTRUCTION FORMATsize of the memory offset follows the address-size default (64 bits in 64-bit mode). See Table 2-6.2.2.1.5 Immediates

3-394 Vol. 2A FSTENV/FNSTENV—Store x87 FPU EnvironmentINSTRUCTION SET REFERENCE, A-M#SS If a memory operand effective address is outside the SS segmen

Vol. 2A 3-395INSTRUCTION SET REFERENCE, A-MFSTSW/FNSTSW—Store x87 FPU Status WordFSTSW/FNSTSW—Store x87 FPU Status WordDescriptionStores the current v

3-396 Vol. 2A FSTSW/FNSTSW—Store x87 FPU Status WordINSTRUCTION SET REFERENCE, A-MIA-32 Architecture CompatibilityWhen operating a Pentium or Intel486

Vol. 2A 3-397INSTRUCTION SET REFERENCE, A-MFSTSW/FNSTSW—Store x87 FPU Status WordVirtual-8086 Mode Exceptions#GP(0) If a memory operand effective addr

3-398 Vol. 2A FSUB/FSUBP/FISUB—SubtractINSTRUCTION SET REFERENCE, A-MFSUB/FSUBP/FISUB—SubtractDescriptionSubtracts the source operand from the destina

Vol. 2A 3-399INSTRUCTION SET REFERENCE, A-MFSUB/FSUBP/FISUB—SubtractThe FISUB instructions convert an integer source operand to double extended-preci-

3-400 Vol. 2A FSUB/FSUBP/FISUB—SubtractINSTRUCTION SET REFERENCE, A-MIF Instruction = FSUBP THEN PopRegisterStack;FI;FPU Flags AffectedC1 Set to 0 if

Vol. 2A 3-401INSTRUCTION SET REFERENCE, A-MFSUB/FSUBP/FISUB—SubtractVirtual-8086 Mode Exceptions#GP(0) If a memory operand effective address is outsid

3-402 Vol. 2A FSUBR/FSUBRP/FISUBR—Reverse SubtractINSTRUCTION SET REFERENCE, A-MFSUBR/FSUBRP/FISUBR—Reverse SubtractDescriptionSubtracts the destinati

Vol. 2A 3-403INSTRUCTION SET REFERENCE, A-MFSUBR/FSUBRP/FISUBR—Reverse Subtractthe register stack being popped. In some assemblers, the mnemonic for t

Vol. 2A 2-15INSTRUCTION FORMATThe ModR/M encoding for RIP-relative addressing does not depend on using prefix. Specifically, the r/m bit field encodin

3-404 Vol. 2A FSUBR/FSUBRP/FISUBR—Reverse SubtractINSTRUCTION SET REFERENCE, A-MIF Instruction = FSUBRP THEN PopRegisterStack; FI;FPU Flags AffectedC1

Vol. 2A 3-405INSTRUCTION SET REFERENCE, A-MFSUBR/FSUBRP/FISUBR—Reverse SubtractVirtual-8086 Mode Exceptions#GP(0) If a memory operand effective addres

3-406 Vol. 2A FTST—TESTINSTRUCTION SET REFERENCE, A-MFTST—TESTDescriptionCompares the value in the ST(0) register with 0.0 and sets the condition code

Vol. 2A 3-407INSTRUCTION SET REFERENCE, A-MFTST—TEST#IA The source operand is a NaN value or is in an unsupported format.#D The source operand is a de

3-408 Vol. 2A FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point ValuesINSTRUCTION SET REFERENCE, A-MFUCOM/FUCOMP/FUCOMPP—Unordered Compare Floatin

Vol. 2A 3-409INSTRUCTION SET REFERENCE, A-MFUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point ValuesThe FUCOMP instruction pops the register stack

3-410 Vol. 2A FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point ValuesINSTRUCTION SET REFERENCE, A-M#IA One or both operands are SNaN values or ha

Vol. 2A 3-411INSTRUCTION SET REFERENCE, A-MFXAM—ExamineModR/MFXAM—ExamineModR/MDescriptionExamines the contents of the ST(0) register and sets the con

3-412 Vol. 2A FXAM—ExamineModR/MINSTRUCTION SET REFERENCE, A-MFPU Flags AffectedC1 Sign of value in ST(0).C0, C2, C3 See Table 3-47.Floating-Point Exc

Vol. 2A 3-413INSTRUCTION SET REFERENCE, A-MFXCH—Exchange Register ContentsFXCH—Exchange Register ContentsDescriptionExchanges the contents of register

2-16 Vol. 2AINSTRUCTION FORMAT

3-414 Vol. 2A FXCH—Exchange Register ContentsINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MF If the

Vol. 2A 3-415INSTRUCTION SET REFERENCE, A-MFXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR StateFXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR StateDescr

3-416 Vol. 2A FXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR StateINSTRUCTION SET REFERENCE, A-Mx87 FPU and SIMD Floating-Point ExceptionsNone.Protecte

Vol. 2A 3-417INSTRUCTION SET REFERENCE, A-MFXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR StateVirtual-8086 Mode ExceptionsSame exceptions as in real a

3-418 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 StateINSTRUCTION SET REFERENCE, A-MFXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2

Vol. 2A 3-419INSTRUCTION SET REFERENCE, A-MFXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 StateThe destination operand contains the first byte of

3-420 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 StateINSTRUCTION SET REFERENCE, A-MTable 3-49. Field Definitions Field DefinitionFCW

Vol. 2A 3-421INSTRUCTION SET REFERENCE, A-MFXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 StateThe FXSAVE instruction saves an abridged version of

3-422 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 StateINSTRUCTION SET REFERENCE, A-MHere, a 1 is saved for any valid, zero, or special

Vol. 2A 3-423INSTRUCTION SET REFERENCE, A-MFXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 StateThe J-bit is defined to be the 1-bit binary integer

Vol. 2A 3-1CHAPTER 3INSTRUCTION SET REFERENCE, A-MThis chapter describes the instruction set for the Intel 64 and IA-32 architectures (A-M) in IA-32e,

3-424 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 StateINSTRUCTION SET REFERENCE, A-MXMM2 192XMM3 208XMM4 224XMM5 240XMM6 256XMM7 272XM

Vol. 2A 3-425INSTRUCTION SET REFERENCE, A-MFXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 StateOperationIF 64-Bit ModeTHENIF REX.W = 1Reserved ST4

3-426 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 StateINSTRUCTION SET REFERENCE, A-MTHENDEST ← Save64BitPromotedFxsave(x87 FPU, MMX, X

Vol. 2A 3-427INSTRUCTION SET REFERENCE, A-MFXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State#UD If CR0.EM[bit 2] = 1.If CPUID.01H:EDX.FXSR[bit

3-428 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 StateINSTRUCTION SET REFERENCE, A-MImplementation NoteThe order in which the processo

Vol. 2A 3-429INSTRUCTION SET REFERENCE, A-MFXTRACT—Extract Exponent and SignificandFXTRACT—Extract Exponent and SignificandDescriptionSeparates the so

3-430 Vol. 2A FXTRACT—Extract Exponent and SignificandINSTRUCTION SET REFERENCE, A-M#IA Source operand is an SNaN value or unsupported format.#Z ST(0)

Vol. 2A 3-431INSTRUCTION SET REFERENCE, A-MFYL2X—Compute y * log2xFYL2X—Compute y ∗ log2xDescriptionComputes (ST(1) ∗ log2 (ST(0))), stores the result

3-432 Vol. 2A FYL2X—Compute y * log2xINSTRUCTION SET REFERENCE, A-MOperationST(1) ← ST(1) ∗ log2ST(0);PopRegisterStack;FPU Flags AffectedC1 Set to 0 i

Vol. 2A 3-433INSTRUCTION SET REFERENCE, A-MFYL2XP1—Compute y * log2(x +1)FYL2XP1—Compute y ∗ log2(x +1)DescriptionComputes (ST(1) ∗ log2(ST(0) + 1.0))

3-2 Vol. 2AINSTRUCTION SET REFERENCE, A-M3.1.1.1 Opcode Column in the Instruction Summary TableThe “Opcode” column in the table above shows the obje

3-434 Vol. 2A FYL2XP1—Compute y * log2(x +1)INSTRUCTION SET REFERENCE, A-Mequation is used to calculate the scale factor for a particular logarithm ba

Vol. 2A 3-435INSTRUCTION SET REFERENCE, A-MHADDPD—Packed Double-FP Horizontal AddHADDPD—Packed Double-FP Horizontal AddDescriptionAdds the double-prec

3-436 Vol. 2A HADDPD—Packed Double-FP Horizontal AddINSTRUCTION SET REFERENCE, A-MOperationxmm1[63:0] = xmm1[63:0] + xmm1[127:64];xmm1[127:64] = xmm2/

Vol. 2A 3-437INSTRUCTION SET REFERENCE, A-MHADDPD—Packed Double-FP Horizontal Add#UD If CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions nu

3-438 Vol. 2A HADDPD—Packed Double-FP Horizontal AddINSTRUCTION SET REFERENCE, A-M#UD If an unmasked SIMD floating-point exception and CR4.OSXM-MEXCP

Vol. 2A 3-439INSTRUCTION SET REFERENCE, A-MHADDPS—Packed Single-FP Horizontal AddHADDPS—Packed Single-FP Horizontal AddDescriptionAdds the single-prec

3-440 Vol. 2A HADDPS—Packed Single-FP Horizontal AddINSTRUCTION SET REFERENCE, A-MIn 64-bit mode, use of the REX.R prefix permits this instruction to

Vol. 2A 3-441INSTRUCTION SET REFERENCE, A-MHADDPS—Packed Single-FP Horizontal AddReal Address Mode ExceptionsGP(0) If any part of the operand would l

3-442 Vol. 2A HADDPS—Packed Single-FP Horizontal AddINSTRUCTION SET REFERENCE, A-M#PF(fault-code) For a page fault.#NM If CR0.TS[bit 3] = 1. #XM If

Vol. 2A 3-443INSTRUCTION SET REFERENCE, A-MHLT—HaltHLT—HaltDescriptionStops instruction execution and places the processor in a HALT state. An enabled

Vol. 2A 3-3INSTRUCTION SET REFERENCE, A-M3.1.1.2 Instruction Column in the Opcode Summary TableThe “Instruction” column gives the syntax of the inst

3-444 Vol. 2A HLT—HaltINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame excep

Vol. 2A 3-445INSTRUCTION SET REFERENCE, A-MHSUBPD—Packed Double-FP Horizontal SubtractHSUBPD—Packed Double-FP Horizontal SubtractDescriptionThe HSUBPD

3-446 Vol. 2A HSUBPD—Packed Double-FP Horizontal SubtractINSTRUCTION SET REFERENCE, A-MOperationxmm1[63:0] = xmm1[63:0] − xmm1[127:64];xmm1[127:64] =

Vol. 2A 3-447INSTRUCTION SET REFERENCE, A-MHSUBPD—Packed Double-FP Horizontal Subtract#UD If CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensi

3-448 Vol. 2A HSUBPD—Packed Double-FP Horizontal SubtractINSTRUCTION SET REFERENCE, A-MIf CPUID feature flag SSE3 is 0.If the LOCK prefix is used.

Vol. 2A 3-449INSTRUCTION SET REFERENCE, A-MHSUBPS—Packed Single-FP Horizontal SubtractHSUBPS—Packed Single-FP Horizontal SubtractDescriptionSubtracts

3-450 Vol. 2A HSUBPS—Packed Single-FP Horizontal SubtractINSTRUCTION SET REFERENCE, A-MIn 64-bit mode, use of the REX.R prefix permits this instructio

Vol. 2A 3-451INSTRUCTION SET REFERENCE, A-MHSUBPS—Packed Single-FP Horizontal SubtractNumeric ExceptionsOverflow, Underflow, Invalid, Precision, Denor

3-452 Vol. 2A HSUBPS—Packed Single-FP Horizontal SubtractINSTRUCTION SET REFERENCE, A-M#NM If CR0.TS[bit 3] = 1.#XM For an unmasked Streaming SIMD E

Vol. 2A 3-453INSTRUCTION SET REFERENCE, A-MIDIV—Signed DivideIDIV—Signed DivideDescriptionDivides the (signed) value in the AX, DX:AX, or EDX:EAX (div

Vol. 2A vCONTENTSPAGECLFLUSH—Flush Cache Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-

3-4 Vol. 2AINSTRUCTION SET REFERENCE, A-M• ptr16:16, ptr16:32 and ptr16:64 — A far pointer, typically to a code segment different from that of the ins

3-454 Vol. 2A IDIV—Signed DivideINSTRUCTION SET REFERENCE, A-MOperationIF SRC = 0THEN #DE; (* Divide error *) FI;IF OperandSize = 8 (* Word/byte opera

Vol. 2A 3-455INSTRUCTION SET REFERENCE, A-MIDIV—Signed DivideTHEN #DE; (* Divide error *) ELSEEAX ← temp;EDX ← EDXE:AX SignedModulus SRC;FI;FI;ELSE IF

3-456 Vol. 2A IDIV—Signed DivideINSTRUCTION SET REFERENCE, A-M#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment l

Vol. 2A 3-457INSTRUCTION SET REFERENCE, A-MIMUL—Signed MultiplyIMUL—Signed MultiplyOpcode Instruction 64-Bit ModeCompat/Leg ModeDescriptionF6 /5 IMUL

3-458 Vol. 2A IMUL—Signed MultiplyINSTRUCTION SET REFERENCE, A-MDescriptionPerforms a signed multiplication of two operands. This instruction has thre

Vol. 2A 3-459INSTRUCTION SET REFERENCE, A-MIMUL—Signed Multiplysigned or unsigned. The CF and OF flags, however, cannot be used to determine if the up

3-460 Vol. 2A IMUL—Signed MultiplyINSTRUCTION SET REFERENCE, A-MELSE IF (NumberOfOperands = 2)THEN temp ← DEST ∗ SRC (* Signed multiplication; temp is

Vol. 2A 3-461INSTRUCTION SET REFERENCE, A-MIMUL—Signed Multiply#SS If a memory operand effective address is outside the SS segment limit.#UD If the L

3-462 Vol. 2A IN—Input from PortINSTRUCTION SET REFERENCE, A-MIN—Input from PortDescriptionCopies the value from the I/O port specified with the secon

Vol. 2A 3-463INSTRUCTION SET REFERENCE, A-MIN—Input from PortDEST ← SRC; (* Read from selected I/O port *)FI;ELSE (Real Mode or Protected Mode with CP

Vol. 2A 3-5INSTRUCTION SET REFERENCE, A-M• r/m32 — A doubleword general-purpose register or memory operand used for instructions whose operand-size at

3-464 Vol. 2A INC—Increment by 1INSTRUCTION SET REFERENCE, A-MINC—Increment by 1DescriptionAdds 1 to the destination operand, while preserving the sta

Vol. 2A 3-465INSTRUCTION SET REFERENCE, A-MINC—Increment by 1Protected Mode Exceptions#GP(0) If the destination operand is located in a non-writable s

3-466 Vol. 2A INC—Increment by 1INSTRUCTION SET REFERENCE, A-M#AC(0) If alignment checking is enabled and an unaligned memory reference is made while

Vol. 2A 3-467INSTRUCTION SET REFERENCE, A-MINS/INSB/INSW/INSD—Input from Port to StringINS/INSB/INSW/INSD—Input from Port to StringDescriptionCopies t

3-468 Vol. 2A INS/INSB/INSW/INSD—Input from Port to StringINSTRUCTION SET REFERENCE, A-Mdestination operand symbol must specify the correct type (size

Vol. 2A 3-469INSTRUCTION SET REFERENCE, A-MINS/INSB/INSW/INSD—Input from Port to StringIF (Byte transfer)THEN IF DF = 0THEN (E)DI ← (E)DI + 1; ELSE (E

3-470 Vol. 2A INS/INSB/INSW/INSD—Input from Port to StringINSTRUCTION SET REFERENCE, A-M#AC(0) If alignment checking is enabled and an unaligned memor

Vol. 2A 3-471INSTRUCTION SET REFERENCE, A-MINT n/INTO/INT 3—Call to Interrupt ProcedureINT n/INTO/INT 3—Call to Interrupt ProcedureDescriptionThe INT

3-472 Vol. 2A INT n/INTO/INT 3—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-Mwith the IRET instruction, which pops the EFLAGS information a

Vol. 2A 3-473INSTRUCTION SET REFERENCE, A-MINT n/INTO/INT 3—Call to Interrupt ProcedureWhen the processor is executing in virtual-8086 mode, the IOPL

3-6 Vol. 2AINSTRUCTION SET REFERENCE, A-M• Sreg — A segment register. The segment register bit assignments are ES = 0, CS = 1, SS = 2, DS = 3, FS = 4,

3-474 Vol. 2A INT n/INTO/INT 3—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-MCS ← IDT(Descriptor (vector_number ∗ 4), selector));EIP ← IDT(

Vol. 2A 3-475INSTRUCTION SET REFERENCE, A-MINT n/INTO/INT 3—Call to Interrupt Procedureor index not within GDT limitsTHEN #GP(TSS selector); FI;Access

3-476 Vol. 2A INT n/INTO/INT 3—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-MIF VM = 1 THEN #GP(new code segment selector); FI;IF code segm

Vol. 2A 3-477INSTRUCTION SET REFERENCE, A-MINT n/INTO/INT 3—Call to Interrupt Procedureor stack segment does not indicate writable data segmentTHEN #T

3-478 Vol. 2A INT n/INTO/INT 3—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-MFI;IF 32-bit gateTHENPush(far pointer to old stack); (* Old SS

Vol. 2A 3-479INSTRUCTION SET REFERENCE, A-MINT n/INTO/INT 3—Call to Interrupt ProcedureNewESP ← stack address;ELSE (* TSS is 16-bit *)TSSstackAddress

3-480 Vol. 2A INT n/INTO/INT 3—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-MTempSS ← SS;TempESP ← ESP;SS:ESP ← TSS(SS0:ESP0); (* Change to

Vol. 2A 3-481INSTRUCTION SET REFERENCE, A-MINT n/INTO/INT 3—Call to Interrupt ProcedureIF instruction pointer not within code segment limitTHEN #GP(0)

3-482 Vol. 2A INT n/INTO/INT 3—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0) If the instruction pointer in

Vol. 2A 3-483INSTRUCTION SET REFERENCE, A-MINT n/INTO/INT 3—Call to Interrupt ProcedureReal-Address Mode Exceptions#GP If a memory operand effective a

Vol. 2A 3-7INSTRUCTION SET REFERENCE, A-M• N.P. — Indicates the REX prefix does not affect the legacy instruction in 64-bit mode.• N.I. — Indicates th

3-484 Vol. 2A INT n/INTO/INT 3—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-MIf the stack segment for the TSS is not a writable data segmen

Vol. 2A 3-485INSTRUCTION SET REFERENCE, A-MINT n/INTO/INT 3—Call to Interrupt Procedure#TS(selector) If an attempt to load RSP from the TSS causes an

3-486 Vol. 2A INVD—Invalidate Internal CachesINSTRUCTION SET REFERENCE, A-MINVD—Invalidate Internal CachesDescriptionInvalidates (flushes) the process

Vol. 2A 3-487INSTRUCTION SET REFERENCE, A-MINVD—Invalidate Internal CachesProtected Mode Exceptions#GP(0) If the current privilege level is not 0.#UD

3-488 Vol. 2A INVLPG—Invalidate TLB EntryINSTRUCTION SET REFERENCE, A-MINVLPG—Invalidate TLB EntryDescriptionInvalidates (flushes) the translation loo

Vol. 2A 3-489INSTRUCTION SET REFERENCE, A-MINVLPG—Invalidate TLB EntryReal-Address Mode Exceptions#UD Operand is a register.If the LOCK prefix is used

3-490 Vol. 2A IRET/IRETD—Interrupt ReturnINSTRUCTION SET REFERENCE, A-MIRET/IRETD—Interrupt ReturnDescriptionReturns program control from an exception

Vol. 2A 3-491INSTRUCTION SET REFERENCE, A-MIRET/IRETD—Interrupt ReturnAs with a real-address mode interrupt return, the IRET instruction pops the retu

3-492 Vol. 2A IRET/IRETD—Interrupt ReturnINSTRUCTION SET REFERENCE, A-MEFLAGS ← (tempEFLAGS AND 257FD5H) OR (EFLAGS AND 1A0000H);ELSE (* OperandSize =

Vol. 2A 3-493INSTRUCTION SET REFERENCE, A-MIRET/IRETD—Interrupt ReturnELSE IF OperandSize = 32THENIF top 12 bytes of stack not within stack limitsTHEN

3-8 Vol. 2AINSTRUCTION SET REFERENCE, A-Maddress contained in register SI relative to the SI register’s default segment (DS) or the overridden segment

3-494 Vol. 2A IRET/IRETD—Interrupt ReturnINSTRUCTION SET REFERENCE, A-MTHEN #GP(0); FI;EIP ← Pop();EIP ← EIP AND 0000FFFFH;CS ← Pop(); (* 16-bit pop *

Vol. 2A 3-495INSTRUCTION SET REFERENCE, A-MIRET/IRETD—Interrupt ReturnIF EIP is not within code segment limit THEN #GP(0); FI;END;PROTECTED-MODE-RETUR

3-496 Vol. 2A IRET/IRETD—Interrupt ReturnINSTRUCTION SET REFERENCE, A-M EFLAGS(IOPL) ← tempEFLAGS; IF OperandSize = 32 or OperandSize = 64THEN EFLAGS(

Vol. 2A 3-497INSTRUCTION SET REFERENCE, A-MIRET/IRETD—Interrupt ReturnIF CPL = 0THENEFLAGS(IOPL) ← tempEFLAGS;IF OperandSize = 32THEN EFLAGS(VM, VIF,

3-498 Vol. 2A IRET/IRETD—Interrupt ReturnINSTRUCTION SET REFERENCE, A-MFlags AffectedAll the flags and fields in the EFLAGS register are potentially m

Vol. 2A 3-499INSTRUCTION SET REFERENCE, A-MIRET/IRETD—Interrupt ReturnVirtual-8086 Mode Exceptions#GP(0) If the return instruction pointer is not with

3-500 Vol. 2A IRET/IRETD—Interrupt ReturnINSTRUCTION SET REFERENCE, A-MIf the stack segment selector RPL is not equal to the RPL of the return code se

Vol. 2A 3-501INSTRUCTION SET REFERENCE, A-MJcc—Jump if Condition Is MetJcc—Jump if Condition Is MetOpcode Instruction 64-Bit ModeCompat/Leg ModeDescri

3-502 Vol. 2A Jcc—Jump if Condition Is MetINSTRUCTION SET REFERENCE, A-M75 cb JNZ rel8 Valid Valid Jump short if not zero (ZF=0).70 cb JO rel8 Valid V

Vol. 2A 3-503INSTRUCTION SET REFERENCE, A-MJcc—Jump if Condition Is Met0F 8C cw JL rel16 N.S. Valid Jump near if less (SF≠ OF). Not supported in 64-bi

Vol. 2A 3-9INSTRUCTION SET REFERENCE, A-MAttribute for Stack” in Chapter 6, “Procedure Calls, Interrupts, and Exceptions,” of the Intel® 64 and IA-32

3-504 Vol. 2A Jcc—Jump if Condition Is MetINSTRUCTION SET REFERENCE, A-M0F 8C cd JNGE rel32 Valid Valid Jump near if not greater or equal (SF≠ OF).0F

Vol. 2A 3-505INSTRUCTION SET REFERENCE, A-MJcc—Jump if Condition Is MetDescriptionChecks the state of one or more of the status flags in the EFLAGS re

3-506 Vol. 2A Jcc—Jump if Condition Is MetINSTRUCTION SET REFERENCE, A-Mchecked is determined by the address-size attribute. These instructions are us

Vol. 2A 3-507INSTRUCTION SET REFERENCE, A-MJcc—Jump if Condition Is MetCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode E

3-508 Vol. 2A JMP—JumpINSTRUCTION SET REFERENCE, A-MJMP—JumpDescriptionTransfers program control to a different point in the instruction stream withou

Vol. 2A 3-509INSTRUCTION SET REFERENCE, A-MJMP—Jump• Short jump—A near jump where the jump range is limited to –128 to +127 from the current EIP value

3-510 Vol. 2A JMP—JumpINSTRUCTION SET REFERENCE, A-M• A task switch.(The JMP instruction cannot be used to perform inter-privilege-level far jumps.)In

Vol. 2A 3-511INSTRUCTION SET REFERENCE, A-MJMP—Jumpand save the previous task link information, allowing a return to the calling task with an IRET ins

3-512 Vol. 2A JMP—JumpINSTRUCTION SET REFERENCE, A-MFI;IF far jump and (PE = 0 or (PE = 1 AND VM = 1)) (* Real-address or virtual-8086 mode *) THEN te

Vol. 2A 3-513INSTRUCTION SET REFERENCE, A-MJMP—JumpTHEN GP(new code segment selector); FI; IF DPL > CPL THEN #GP(segment selector); FI; IF segment

3-10 Vol. 2AINSTRUCTION SET REFERENCE, A-Mzero (00H); if it is greater than 65535, it is represented by the saturated value 65535 (FFFFH).• LowOrderWo

3-514 Vol. 2A JMP—JumpINSTRUCTION SET REFERENCE, A-MTHEN #GP(0); FI;IF call gate code-segment selector index outside descriptor table limitsTHEN #GP(c

Vol. 2A 3-515INSTRUCTION SET REFERENCE, A-MJMP—Jumpor TSS DPL < TSS segment-selector RPLor TSS descriptor indicates TSS not availableTHEN #GP(TSS s

3-516 Vol. 2A JMP—JumpINSTRUCTION SET REFERENCE, A-MIf the segment selector for a TSS has its local/global bit set for local.If a TSS segment descript

Vol. 2A 3-517INSTRUCTION SET REFERENCE, A-MJMP—JumpIf target offset in destination operand is non-canonical.If target offset in destination operand is

3-518 Vol. 2A LAHF—Load Status Flags into AH RegisterINSTRUCTION SET REFERENCE, A-MLAHF—Load Status Flags into AH RegisterDescriptionThis instruction

Vol. 2A 3-519INSTRUCTION SET REFERENCE, A-MLAHF—Load Status Flags into AH Register64-Bit Mode Exceptions#UD If CPUID.80000001H:ECX.LAHF-SAHF[bit 0] =

3-520 Vol. 2A LAR—Load Access Rights ByteINSTRUCTION SET REFERENCE, A-MLAR—Load Access Rights ByteDescriptionLoads the access rights from the segment

Vol. 2A 3-521INSTRUCTION SET REFERENCE, A-MLAR—Load Access Rights Byte• If the segment is not a conforming code segment, it checks that the specified

3-522 Vol. 2A LAR—Load Access Rights ByteINSTRUCTION SET REFERENCE, A-MZF = 0; ELSE IF SegmentDescriptor(Type) ≠ conforming code segmentand (CPL >

Vol. 2A 3-523INSTRUCTION SET REFERENCE, A-MLAR—Load Access Rights ByteVirtual-8086 Mode Exceptions#UD The LAR instruction cannot be executed in virtua

Vol. 2A 3-11INSTRUCTION SET REFERENCE, A-MThe addressed bit is numbered (Offset MOD 8) within the byte at address (BitBase + (BitOffset DIV 8)) where

3-524 Vol. 2A LDDQU—Load Unaligned Integer 128 BitsINSTRUCTION SET REFERENCE, A-MLDDQU—Load Unaligned Integer 128 BitsDescriptionThe instruction is fu

Vol. 2A 3-525INSTRUCTION SET REFERENCE, A-MLDDQU—Load Unaligned Integer 128 BitsIntel C/C++ Compiler Intrinsic EquivalentLDDQU __m128i _mm_lddqu_si128

3-526 Vol. 2A LDDQU—Load Unaligned Integer 128 BitsINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-

Vol. 2A 3-527INSTRUCTION SET REFERENCE, A-MLDMXCSR—Load MXCSR RegisterLDMXCSR—Load MXCSR RegisterDescriptionLoads the source operand into the MXCSR co

3-528 Vol. 2A LDMXCSR—Load MXCSR RegisterINSTRUCTION SET REFERENCE, A-MIf CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0) If alignment

Vol. 2A 3-529INSTRUCTION SET REFERENCE, A-MLDS/LES/LFS/LGS/LSS—Load Far PointerLDS/LES/LFS/LGS/LSS—Load Far PointerDescriptionLoads a far pointer (seg

3-530 Vol. 2A LDS/LES/LFS/LGS/LSS—Load Far PointerINSTRUCTION SET REFERENCE, A-MIf one of these instructions is executed in protected mode, additional

Vol. 2A 3-531INSTRUCTION SET REFERENCE, A-MLDS/LES/LFS/LGS/LSS—Load Far PointerFI;SegmentRegister ← SegmentSelector(SRC) ;SegmentRegister ← SegmentDes

3-532 Vol. 2A LDS/LES/LFS/LGS/LSS—Load Far PointerINSTRUCTION SET REFERENCE, A-MFI;DEST ← Offset(SRC);Real-Address or Virtual-8086 ModeSegmentRegister

Vol. 2A 3-533INSTRUCTION SET REFERENCE, A-MLDS/LES/LFS/LGS/LSS—Load Far Pointer#SS If a memory operand effective address is outside the SS segment lim

3-12 Vol. 2AINSTRUCTION SET REFERENCE, A-MSee Appendix C, “InteL® C/C++ Compiler Intrinsics and Functional Equivalents,” in the Intel® 64 and IA-32 Ar

3-534 Vol. 2A LDS/LES/LFS/LGS/LSS—Load Far PointerINSTRUCTION SET REFERENCE, A-M#NP(selector) If FS, or GS register is being loaded with a non-NULL se

Vol. 2A 3-535INSTRUCTION SET REFERENCE, A-MLEA—Load Effective AddressLEA—Load Effective AddressDescriptionComputes the effective address of the second

3-536 Vol. 2A LEA—Load Effective AddressINSTRUCTION SET REFERENCE, A-MOperationIF OperandSize = 16 and AddressSize = 16THEN DEST ← EffectiveAddress(SR

Vol. 2A 3-537INSTRUCTION SET REFERENCE, A-MLEA—Load Effective AddressDEST ← temp[0:15]; (* 16-bit address *)FI;ELSE IF OperandSize = 32 and AddressSiz

3-538 Vol. 2A LEAVE—High Level Procedure ExitINSTRUCTION SET REFERENCE, A-MLEAVE—High Level Procedure ExitDescriptionReleases the stack frame set up b

Vol. 2A 3-539INSTRUCTION SET REFERENCE, A-MLEAVE—High Level Procedure ExitFlags AffectedNone.Protected Mode Exceptions#SS(0) If the EBP register point

3-540 Vol. 2A LFENCE—Load FenceINSTRUCTION SET REFERENCE, A-MLFENCE—Load FenceDescriptionPerforms a serializing operation on all load-from-memory inst

Vol. 2A 3-541INSTRUCTION SET REFERENCE, A-MLGDT/LIDT—Load Global/Interrupt Descriptor Table RegisterLGDT/LIDT—Load Global/Interrupt Descriptor Table R

3-542 Vol. 2A LGDT/LIDT—Load Global/Interrupt Descriptor Table RegisterINSTRUCTION SET REFERENCE, A-MIDTR(Limit) ← SRC[0:15];IDTR(Base) ← SRC[16:47];

Vol. 2A 3-543INSTRUCTION SET REFERENCE, A-MLGDT/LIDT—Load Global/Interrupt Descriptor Table RegisterReal-Address Mode Exceptions#UD If source operand

Vol. 2A 3-13INSTRUCTION SET REFERENCE, A-M• The __m128i data type can hold sixteen byte, eight word, or four doubleword, or two quadword integer value

3-544 Vol. 2A LLDT—Load Local Descriptor Table RegisterINSTRUCTION SET REFERENCE, A-MLLDT—Load Local Descriptor Table RegisterDescriptionLoads the sou

Vol. 2A 3-545INSTRUCTION SET REFERENCE, A-MLLDT—Load Local Descriptor Table RegisterELSE LDTR ← INVALIDFI;Flags AffectedNone.Protected Mode Exceptions

3-546 Vol. 2A LLDT—Load Local Descriptor Table RegisterINSTRUCTION SET REFERENCE, A-M#PF(fault-code) If a page fault occurs.#UD If the LOCK prefix is

Vol. 2A 3-547INSTRUCTION SET REFERENCE, A-MLMSW—Load Machine Status WordLMSW—Load Machine Status WordDescriptionLoads the source operand into the mach

3-548 Vol. 2A LMSW—Load Machine Status WordINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0) If the current privilege level is not 0.If a

Vol. 2A 3-549INSTRUCTION SET REFERENCE, A-MLOCK—Assert LOCK# Signal PrefixLOCK—Assert LOCK# Signal PrefixDescriptionCauses the processor’s LOCK# signa

3-550 Vol. 2A LOCK—Assert LOCK# Signal PrefixINSTRUCTION SET REFERENCE, A-MOperationAssertLOCK#(DurationOfAccompaningInstruction);Flags AffectedNone.P

Vol. 2A 3-551INSTRUCTION SET REFERENCE, A-MLODS/LODSB/LODSW/LODSD/LODSQ—Load StringLODS/LODSB/LODSW/LODSD/LODSQ—Load StringDescriptionLoads a byte, wo

3-552 Vol. 2A LODS/LODSB/LODSW/LODSD/LODSQ—Load StringINSTRUCTION SET REFERENCE, A-Mcorrect location. The location is always specified by the DS:(E)SI

Vol. 2A 3-553INSTRUCTION SET REFERENCE, A-MLODS/LODSB/LODSW/LODSD/LODSQ—Load StringFI;FI;ELSE IF RAX ← SRC; (* Quadword load *)THEN IF DF = 0THEN (R)S

CONTENTSviVol. 2APAGEDouble-Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-231CVTSS2SI—Conver

3-14 Vol. 2AINSTRUCTION SET REFERENCE, A-MSome intrinsics are “composites” because they require more than one instruction to implement them. You shoul

3-554 Vol. 2A LODS/LODSB/LODSW/LODSD/LODSQ—Load StringINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.

Vol. 2A 3-555INSTRUCTION SET REFERENCE, A-MLOOP/LOOPcc—Loop According to ECX CounterLOOP/LOOPcc—Loop According to ECX CounterDescriptionPerforms a loo

3-556 Vol. 2A LOOP/LOOPcc—Loop According to ECX CounterINSTRUCTION SET REFERENCE, A-MIF (Instruction ← LOOPE) or (Instruction ← LOOPZ)THEN IF (ZF = 1)

Vol. 2A 3-557INSTRUCTION SET REFERENCE, A-MLOOP/LOOPcc—Loop According to ECX CounterProtected Mode Exceptions#GP(0) If the offset being jumped to is b

3-558 Vol. 2A LSL—Load Segment LimitINSTRUCTION SET REFERENCE, A-MLSL—Load Segment LimitDescriptionLoads the unscrambled segment limit from the segmen

Vol. 2A 3-559INSTRUCTION SET REFERENCE, A-MLSL—Load Segment Limit• Checks that the descriptor type is valid for this instruction. All code and data se

3-560 Vol. 2A LSL—Load Segment LimitINSTRUCTION SET REFERENCE, A-MRead segment descriptor;IF SegmentDescriptor(Type) ≠ conforming code segmentand (CPL

Vol. 2A 3-561INSTRUCTION SET REFERENCE, A-MLSL—Load Segment LimitCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Excepti

3-562 Vol. 2A LTR—Load Task RegisterINSTRUCTION SET REFERENCE, A-MLTR—Load Task RegisterDescriptionLoads the source operand into the segment selector

Vol. 2A 3-563INSTRUCTION SET REFERENCE, A-MLTR—Load Task RegisterFlags AffectedNone.Protected Mode Exceptions#GP(0) If the current privilege level is

Vol. 2A 3-15INSTRUCTION SET REFERENCE, A-Mletter mnemonic with the corresponding interrupt vector number and exception name. See Chapter 5, “Interrupt

3-564 Vol. 2A LTR—Load Task RegisterINSTRUCTION SET REFERENCE, A-M#NP(selector) If the TSS is marked not present.#PF(fault-code) If a page fault occur

Vol. 2A 3-565INSTRUCTION SET REFERENCE, A-MMASKMOVDQU—Store Selected Bytes of Double QuadwordMASKMOVDQU—Store Selected Bytes of Double QuadwordDescrip

3-566 Vol. 2A MASKMOVDQU—Store Selected Bytes of Double QuadwordINSTRUCTION SET REFERENCE, A-MIn 64-bit mode, use of the REX.R prefix permits this ins

Vol. 2A 3-567INSTRUCTION SET REFERENCE, A-MMASKMOVDQU—Store Selected Bytes of Double QuadwordVirtual-8086 Mode ExceptionsSame exceptions as in real ad

3-568 Vol. 2A MASKMOVQ—Store Selected Bytes of QuadwordINSTRUCTION SET REFERENCE, A-MMASKMOVQ—Store Selected Bytes of QuadwordDescriptionStores select

Vol. 2A 3-569INSTRUCTION SET REFERENCE, A-MMASKMOVQ—Store Selected Bytes of QuadwordThe MASKMOVQ instruction can be used to improve performance for al

3-570 Vol. 2A MASKMOVQ—Store Selected Bytes of QuadwordINSTRUCTION SET REFERENCE, A-M#MF If there is a pending FPU exception.#UD If CR0.EM[bit 2] = 1

Vol. 2A 3-571INSTRUCTION SET REFERENCE, A-MMAXPD—Return Maximum Packed Double-Precision Floating-Point ValuesMAXPD—Return Maximum Packed Double-Precis

3-572 Vol. 2A MAXPD—Return Maximum Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MELSE SRC[127:64]; FI; FI;Intel C/C++ Com

Vol. 2A 3-573INSTRUCTION SET REFERENCE, A-MMAXPD—Return Maximum Packed Double-Precision Floating-Point ValuesVirtual-8086 Mode ExceptionsSame exceptio

3-16 Vol. 2AINSTRUCTION SET REFERENCE, A-M3.1.1.12 Real-Address Mode Exceptions SectionThe “Real-Address Mode Exceptions” section lists the exceptio

3-574 Vol. 2A MAXPS—Return Maximum Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MMAXPS—Return Maximum Packed Single-Preci

Vol. 2A 3-575INSTRUCTION SET REFERENCE, A-MMAXPS—Return Maximum Packed Single-Precision Floating-Point ValuesTHEN DEST[127:96]; ELSE SRC[127:96]; FI;

3-576 Vol. 2A MAXPS—Return Maximum Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MIf CPUID.01H:EDX.SSE[bit 25] = 0.If the

Vol. 2A 3-577INSTRUCTION SET REFERENCE, A-MMAXSD—Return Maximum Scalar Double-Precision Floating-Point ValueMAXSD—Return Maximum Scalar Double-Precisi

3-578 Vol. 2A MAXSD—Return Maximum Scalar Double-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MIntel C/C++ Compiler Intrinsic Equivalent

Vol. 2A 3-579INSTRUCTION SET REFERENCE, A-MMAXSD—Return Maximum Scalar Double-Precision Floating-Point Value#PF(fault-code) For a page fault.#AC(0) I

3-580 Vol. 2A MAXSS—Return Maximum Scalar Single-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MMAXSS—Return Maximum Scalar Single-Precis

Vol. 2A 3-581INSTRUCTION SET REFERENCE, A-MMAXSS—Return Maximum Scalar Single-Precision Floating-Point ValueSIMD Floating-Point ExceptionsInvalid (inc

3-582 Vol. 2A MAXSS—Return Maximum Scalar Single-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame excepti

Vol. 2A 3-583INSTRUCTION SET REFERENCE, A-MMFENCE—Memory FenceMFENCE—Memory FenceDescriptionPerforms a serializing operation on all load-from-memory a

Vol. 2A 3-17INSTRUCTION SET REFERENCE, A-M3.1.1.15 SIMD Floating-Point Exceptions SectionThe “SIMD Floating-Point Exceptions” section lists exceptio

3-584 Vol. 2A MINPD—Return Minimum Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MMINPD—Return Minimum Packed Double-Preci

Vol. 2A 3-585INSTRUCTION SET REFERENCE, A-MMINPD—Return Minimum Packed Double-Precision Floating-Point ValuesTHEN DEST[127:64] ELSE SRC[127:64]; FI; F

3-586 Vol. 2A MINPD—Return Minimum Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MIf CPUID.01H:EDX.SSE2[bit 26] = 0.If the

Vol. 2A 3-587INSTRUCTION SET REFERENCE, A-MMINPS—Return Minimum Packed Single-Precision Floating-Point ValuesMINPS—Return Minimum Packed Single-Precis

3-588 Vol. 2A MINPS—Return Minimum Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MTHEN DEST[127:96] ELSE SRC[127:96]; FI;

Vol. 2A 3-589INSTRUCTION SET REFERENCE, A-MMINPS—Return Minimum Packed Single-Precision Floating-Point ValuesIf CPUID.01H:EDX.SSE[bit 25] = 0.If the L

3-590 Vol. 2A MINSD—Return Minimum Scalar Double-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MMINSD—Return Minimum Scalar Double-Precis

Vol. 2A 3-591INSTRUCTION SET REFERENCE, A-MMINSD—Return Minimum Scalar Double-Precision Floating-Point ValueSIMD Floating-Point ExceptionsInvalid (inc

3-592 Vol. 2A MINSD—Return Minimum Scalar Double-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame excepti

Vol. 2A 3-593INSTRUCTION SET REFERENCE, A-MMINSS—Return Minimum Scalar Single-Precision Floating-Point ValueMINSS—Return Minimum Scalar Single-Precisi

3-18 Vol. 2AINSTRUCTION SET REFERENCE, A-M3.2 INSTRUCTIONS (A-M)The remainder of this chapter provides descriptions of Intel 64 and IA-32 instructions

3-594 Vol. 2A MINSS—Return Minimum Scalar Single-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsInvalid (in

Vol. 2A 3-595INSTRUCTION SET REFERENCE, A-MMINSS—Return Minimum Scalar Single-Precision Floating-Point ValueCompatibility Mode ExceptionsSame exceptio

3-596 Vol. 2A MONITOR—Set Up Monitor AddressINSTRUCTION SET REFERENCE, A-MMONITOR—Set Up Monitor AddressDescriptionThe MONITOR instruction arms addres

Vol. 2A 3-597INSTRUCTION SET REFERENCE, A-MMONITOR—Set Up Monitor AddressOperationMONITOR sets up an address range for the monitor hardware using the

3-598 Vol. 2A MONITOR—Set Up Monitor AddressINSTRUCTION SET REFERENCE, A-M64-Bit Mode Exceptions#GP(0) If the linear address of the operand in the CS,

Vol. 2A 3-599INSTRUCTION SET REFERENCE, A-MMOV—MoveMOV—MoveOpcode Instruction 64-Bit ModeCompat/Leg ModeDescription88 /r MOV r/m8,r8 Valid Valid Move

3-600 Vol. 2A MOV—MoveINSTRUCTION SET REFERENCE, A-MDescriptionCopies the second operand (source operand) to the first operand (destination operand).

Vol. 2A 3-601INSTRUCTION SET REFERENCE, A-MMOV—Movebelow). The segment descriptor data is obtained from the GDT or LDT entry for the specified segment

3-602 Vol. 2A MOV—MoveINSTRUCTION SET REFERENCE, A-MLoading a segment register while in protected mode results in special checks and actions, as descr

Vol. 2A 3-603INSTRUCTION SET REFERENCE, A-MMOV—MoveProtected Mode Exceptions#GP(0) If attempt is made to load SS register with NULL segment selector.I

Vol. 2A 3-19INSTRUCTION SET REFERENCE, A-MAAA—ASCII Adjust After AdditionAAA—ASCII Adjust After AdditionDescriptionAdjusts the sum of two unpacked BCD

3-604 Vol. 2A MOV—MoveINSTRUCTION SET REFERENCE, A-M#SS(0) If a memory operand effective address is outside the SS segment limit.#PF(fault-code) If a

Vol. 2A 3-605INSTRUCTION SET REFERENCE, A-MMOV—Move to/from Control RegistersMOV—Move to/from Control RegistersDescriptionMoves the contents of a cont

3-606 Vol. 2A MOV—Move to/from Control RegistersINSTRUCTION SET REFERENCE, A-Mand CR3 remain clear after any load of those registers; attempts to set

Vol. 2A 3-607INSTRUCTION SET REFERENCE, A-MMOV—Move to/from Control RegistersIf an attempt is made to write invalid bit combinations in CR0 (such as s

3-608 Vol. 2A MOV—Move to/from Debug RegistersINSTRUCTION SET REFERENCE, A-MMOV—Move to/from Debug RegistersDescriptionMoves the contents of a debug r

Vol. 2A 3-609INSTRUCTION SET REFERENCE, A-MMOV—Move to/from Debug RegistersFlags AffectedThe OF, SF, ZF, AF, PF, and CF flags are undefined.Protected

3-610 Vol. 2A MOVAPD—Move Aligned Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MMOVAPD—Move Aligned Packed Double-Precisi

Vol. 2A 3-611INSTRUCTION SET REFERENCE, A-MMOVAPD—Move Aligned Packed Double-Precision Floating-Point ValuesProtected Mode Exceptions#GP(0) For an ill

3-612 Vol. 2A MOVAPD—Move Aligned Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#UD If CR0.EM[bit 2] = 1.If CR4.OSFXSR[b

Vol. 2A 3-613INSTRUCTION SET REFERENCE, A-MMOVAPS—Move Aligned Packed Single-Precision Floating-Point ValuesMOVAPS—Move Aligned Packed Single-Precisio

3-20 Vol. 2A AAA—ASCII Adjust After AdditionINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#UD If the LOCK prefix is used.Real-Address Mode Ex

3-614 Vol. 2A MOVAPS—Move Aligned Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0) For an il

Vol. 2A 3-615INSTRUCTION SET REFERENCE, A-MMOVAPS—Move Aligned Packed Single-Precision Floating-Point Values#UD If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bi

3-616 Vol. 2A MOVD/MOVQ—Move Doubleword/Move QuadwordINSTRUCTION SET REFERENCE, A-MMOVD/MOVQ—Move Doubleword/Move QuadwordDescriptionCopies a doublewo

Vol. 2A 3-617INSTRUCTION SET REFERENCE, A-MMOVD/MOVQ—Move Doubleword/Move QuadwordOperationMOVD instruction when destination operand is MMX technology

3-618 Vol. 2A MOVD/MOVQ—Move Doubleword/Move QuadwordINSTRUCTION SET REFERENCE, A-M#UD If CR0.EM[bit 2] = 1.128-bit operations will generate #UD only

Vol. 2A 3-619INSTRUCTION SET REFERENCE, A-MMOVD/MOVQ—Move Doubleword/Move Quadword#UD If CR0.EM[bit 2] = 1.(XMM register operations only) if CR4.OSFXS

3-620 Vol. 2A MOVDDUP—Move One Double-FP and DuplicateINSTRUCTION SET REFERENCE, A-MMOVDDUP—Move One Double-FP and DuplicateDescriptionThe linear addr

Vol. 2A 3-621INSTRUCTION SET REFERENCE, A-MMOVDDUP—Move One Double-FP and Duplicatexmm1[127:64] = m64; ELSE (* Move instruction *)xmm1[63:0] = xmm2[63

3-622 Vol. 2A MOVDDUP—Move One Double-FP and DuplicateINSTRUCTION SET REFERENCE, A-MVirtual 8086 Mode ExceptionsGP(0) If any part of the operand woul

Vol. 2A 3-623INSTRUCTION SET REFERENCE, A-MMOVDQA—Move Aligned Double QuadwordMOVDQA—Move Aligned Double QuadwordDescriptionMoves a double quadword fr

Vol. 2A 3-21INSTRUCTION SET REFERENCE, A-MAAD—ASCII Adjust AX Before DivisionAAD—ASCII Adjust AX Before DivisionDescriptionAdjusts two unpacked BCD di

3-624 Vol. 2A MOVDQA—Move Aligned Double QuadwordINSTRUCTION SET REFERENCE, A-M#SS(0) If a memory operand effective address is outside the SS segment

Vol. 2A 3-625INSTRUCTION SET REFERENCE, A-MMOVDQU—Move Unaligned Double QuadwordMOVDQU—Move Unaligned Double QuadwordDescriptionMoves a double quadwor

3-626 Vol. 2A MOVDQU—Move Unaligned Double QuadwordINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#AC(0) If alignment checking is enabled and

Vol. 2A 3-627INSTRUCTION SET REFERENCE, A-MMOVDQU—Move Unaligned Double Quadword#UD If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SS

3-628 Vol. 2A MOVDQ2Q—Move Quadword from XMM to MMX Technology RegisterINSTRUCTION SET REFERENCE, A-MMOVDQ2Q—Move Quadword from XMM to MMX Technology

Vol. 2A 3-629INSTRUCTION SET REFERENCE, A-MMOVDQ2Q—Move Quadword from XMM to MMX Technology RegisterVirtual-8086 Mode ExceptionsSame exceptions as in

3-630 Vol. 2A MOVHLPS— Move Packed Single-Precision Floating-Point Values High to LowINSTRUCTION SET REFERENCE, A-MMOVHLPS— Move Packed Single-Precisi

Vol. 2A 3-631INSTRUCTION SET REFERENCE, A-MMOVHLPS— Move Packed Single-Precision Floating-Point Values High to LowVirtual 8086 Mode ExceptionsSame exc

3-632 Vol. 2A MOVHPD—Move High Packed Double-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MMOVHPD—Move High Packed Double-Precision Floa

Vol. 2A 3-633INSTRUCTION SET REFERENCE, A-MMOVHPD—Move High Packed Double-Precision Floating-Point ValueProtected Mode Exceptions#GP(0) For an illegal

3-22 Vol. 2A AAD—ASCII Adjust AX Before DivisionINSTRUCTION SET REFERENCE, A-MFlags AffectedThe SF, ZF, and PF flags are set according to the resultin

3-634 Vol. 2A MOVHPD—Move High Packed Double-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MIf CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK

Vol. 2A 3-635INSTRUCTION SET REFERENCE, A-MMOVHPS—Move High Packed Single-Precision Floating-Point ValuesMOVHPS—Move High Packed Single-Precision Floa

3-636 Vol. 2A MOVHPS—Move High Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#SS(0) For an illegal address in the SS seg

Vol. 2A 3-637INSTRUCTION SET REFERENCE, A-MMOVHPS—Move High Packed Single-Precision Floating-Point Values#AC(0) If alignment checking is enabled and a

3-638 Vol. 2A MOVLHPS—Move Packed Single-Precision Floating-Point Values Low to HighINSTRUCTION SET REFERENCE, A-MMOVLHPS—Move Packed Single-Precision

Vol. 2A 3-639INSTRUCTION SET REFERENCE, A-MMOVLHPS—Move Packed Single-Precision Floating-Point Values Low to HighCompatibility Mode ExceptionsSame exc

3-640 Vol. 2A MOVLPD—Move Low Packed Double-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MMOVLPD—Move Low Packed Double-Precision Floati

Vol. 2A 3-641INSTRUCTION SET REFERENCE, A-MMOVLPD—Move Low Packed Double-Precision Floating-Point Value#SS(0) For an illegal address in the SS segmen

3-642 Vol. 2A MOVLPS—Move Low Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MMOVLPS—Move Low Packed Single-Precision Float

Vol. 2A 3-643INSTRUCTION SET REFERENCE, A-MMOVLPS—Move Low Packed Single-Precision Floating-Point Values#SS(0) For an illegal address in the SS segme

Vol. 2A 3-23INSTRUCTION SET REFERENCE, A-MAAM—ASCII Adjust AX After MultiplyAAM—ASCII Adjust AX After MultiplyDescriptionAdjusts the result of the mul

3-644 Vol. 2A MOVLPS—Move Low Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#AC(0) If alignment checking is enabled and a

Vol. 2A 3-645INSTRUCTION SET REFERENCE, A-MMOVMSKPD—Extract Packed Double-Precision Floating-Point Sign MaskMOVMSKPD—Extract Packed Double-Precision F

3-646 Vol. 2A MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign MaskINSTRUCTION SET REFERENCE, A-M#UD If CR0.EM[bit 2] = 1.If CR4.OSFXSR[b

Vol. 2A 3-647INSTRUCTION SET REFERENCE, A-MMOVMSKPS—Extract Packed Single-Precision Floating-Point Sign MaskMOVMSKPS—Extract Packed Single-Precision F

3-648 Vol. 2A MOVMSKPS—Extract Packed Single-Precision Floating-Point Sign MaskINSTRUCTION SET REFERENCE, A-M#UD If CR0.EM[bit 2] = 1.If CR4.OSFXSR[b

Vol. 2A 3-649INSTRUCTION SET REFERENCE, A-MMOVNTDQ—Store Double Quadword Using Non-Temporal HintMOVNTDQ—Store Double Quadword Using Non-Temporal HintD

3-650 Vol. 2A MOVNTDQ—Store Double Quadword Using Non-Temporal HintINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0) For an illegal memory

Vol. 2A 3-651INSTRUCTION SET REFERENCE, A-MMOVNTDQ—Store Double Quadword Using Non-Temporal Hint#UD If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If C

3-652 Vol. 2A MOVNTI—Store Doubleword Using Non-Temporal HintINSTRUCTION SET REFERENCE, A-MMOVNTI—Store Doubleword Using Non-Temporal HintDescriptionM

Vol. 2A 3-653INSTRUCTION SET REFERENCE, A-MMOVNTI—Store Doubleword Using Non-Temporal HintProtected Mode Exceptions#GP(0) For an illegal memory operan

Vol. 2A viiCONTENTSPAGEFLD—Load Floating Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3-24 Vol. 2A AAM—ASCII Adjust AX After MultiplyINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#DE If an immediate value of 0 is used.#UD If t

3-654 Vol. 2A MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-TemporalHintINSTRUCTION SET REFERENCE, A-MMOVNTPD—Store Packed Dou

Vol. 2A 3-655INSTRUCTION SET REFERENCE, A-MMOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-Temporal HintProtected Mode Exception

3-656 Vol. 2A MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-TemporalHintINSTRUCTION SET REFERENCE, A-M#UD If CR0.EM[bit 2] = 1

Vol. 2A 3-657INSTRUCTION SET REFERENCE, A-MMOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal HintMOVNTPS—Store Packed Sin

3-658 Vol. 2A MOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-TemporalHintINSTRUCTION SET REFERENCE, A-MProtected Mode Exception

Vol. 2A 3-659INSTRUCTION SET REFERENCE, A-MMOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint#UD If CR0.EM[bit 2] = 1

3-660 Vol. 2A MOVNTQ—Store of Quadword Using Non-Temporal HintINSTRUCTION SET REFERENCE, A-MMOVNTQ—Store of Quadword Using Non-Temporal HintDescriptio

Vol. 2A 3-661INSTRUCTION SET REFERENCE, A-MMOVNTQ—Store of Quadword Using Non-Temporal Hint#SS(0) For an illegal address in the SS segment. #PF(fault

3-662 Vol. 2A MOVNTQ—Store of Quadword Using Non-Temporal HintINSTRUCTION SET REFERENCE, A-M#UD If CR0.EM[bit 2] = 1.If CPUID.01H:EDX.SSE[bit 25] = 0.

Vol. 2A 3-663INSTRUCTION SET REFERENCE, A-MMOVQ—Move QuadwordMOVQ—Move QuadwordDescriptionCopies a quadword from the source operand (second operand) t

Vol. 2A 3-25INSTRUCTION SET REFERENCE, A-MAAS—ASCII Adjust AL After SubtractionAAS—ASCII Adjust AL After SubtractionDescriptionAdjusts the result of t

3-664 Vol. 2A MOVQ—Move QuadwordINSTRUCTION SET REFERENCE, A-MDEST[127:64] ← 0000000000000000H;Flags AffectedNone.SIMD Floating-Point ExceptionsNone.P

Vol. 2A 3-665INSTRUCTION SET REFERENCE, A-MMOVQ—Move QuadwordVirtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code) If a

3-666 Vol. 2A MOVQ2DQ—Move Quadword from MMX Technology to XMM RegisterINSTRUCTION SET REFERENCE, A-MMOVQ2DQ—Move Quadword from MMX Technology to XMM

Vol. 2A 3-667INSTRUCTION SET REFERENCE, A-MMOVQ2DQ—Move Quadword from MMX Technology to XMM RegisterVirtual-8086 Mode ExceptionsSame exceptions as in

3-668 Vol. 2A MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to StringINSTRUCTION SET REFERENCE, A-MMOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from St

Vol. 2A 3-669INSTRUCTION SET REFERENCE, A-MMOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to StringAt the assembly-code level, two forms of this i

3-670 Vol. 2A MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to StringINSTRUCTION SET REFERENCE, A-M(E)SI ← (E)SI – 1; (E)DI ← (E)DI – 1; FI;ELSE

Vol. 2A 3-671INSTRUCTION SET REFERENCE, A-MMOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String(R|E)SI ← (R|E)SI + 4; (R|E)DI ← (R|E)DI + 4; F

3-672 Vol. 2A MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to StringINSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode Exceptions#GP(0) If a memory

Vol. 2A 3-673INSTRUCTION SET REFERENCE, A-MMOVSD—Move Scalar Double-Precision Floating-Point ValueMOVSD—Move Scalar Double-Precision Floating-Point Va

3-26 Vol. 2A AAS—ASCII Adjust AL After SubtractionINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#UD If the LOCK prefix is used.Real-Address

3-674 Vol. 2A MOVSD—Move Scalar Double-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MMOVSD void _mm_store_sd (double *p, __m128d a)MOVSD

Vol. 2A 3-675INSTRUCTION SET REFERENCE, A-MMOVSD—Move Scalar Double-Precision Floating-Point Value64-Bit Mode Exceptions#SS(0) If a memory address ref

3-676 Vol. 2A MOVSHDUP—Move Packed Single-FP High and DuplicateINSTRUCTION SET REFERENCE, A-MMOVSHDUP—Move Packed Single-FP High and DuplicateDescript

Vol. 2A 3-677INSTRUCTION SET REFERENCE, A-MMOVSHDUP—Move Packed Single-FP High and DuplicateOperationIF (Source == m128) THEN (* Load instruction *)x

3-678 Vol. 2A MOVSHDUP—Move Packed Single-FP High and DuplicateINSTRUCTION SET REFERENCE, A-MReal Address Mode ExceptionsGP(0) If any part of the ope

Vol. 2A 3-679INSTRUCTION SET REFERENCE, A-MMOVSLDUP—Move Packed Single-FP Low and DuplicateMOVSLDUP—Move Packed Single-FP Low and DuplicateDescription

3-680 Vol. 2A MOVSLDUP—Move Packed Single-FP Low and DuplicateINSTRUCTION SET REFERENCE, A-MOperationIF (Source == m128) THEN (* Load instruction *)x

Vol. 2A 3-681INSTRUCTION SET REFERENCE, A-MMOVSLDUP—Move Packed Single-FP Low and DuplicateReal Address Mode ExceptionsGP(0) If any part of the opera

3-682 Vol. 2A MOVSS—Move Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MMOVSS—Move Scalar Single-Precision Floating-Point

Vol. 2A 3-683INSTRUCTION SET REFERENCE, A-MMOVSS—Move Scalar Single-Precision Floating-Point ValuesMOVSS void _mm_store_ss(float * p, __m128 a)MOVSS _

Vol. 2A 3-27INSTRUCTION SET REFERENCE, A-MADC—Add with CarryADC—Add with CarryOpcode Instruction 64-Bit ModeCompat/Leg ModeDescription14 ib ADC AL, im

3-684 Vol. 2A MOVSS—Move Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M64-Bit Mode Exceptions#SS(0) If a memory address r

Vol. 2A 3-685INSTRUCTION SET REFERENCE, A-MMOVSX/MOVSXD—Move with Sign-ExtensionMOVSX/MOVSXD—Move with Sign-ExtensionDescriptionCopies the contents of

3-686 Vol. 2A MOVSX/MOVSXD—Move with Sign-ExtensionINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0) If a memory operand effective address

Vol. 2A 3-687INSTRUCTION SET REFERENCE, A-MMOVUPD—Move Unaligned Packed Double-Precision Floating-Point ValuesMOVUPD—Move Unaligned Packed Double-Prec

3-688 Vol. 2A MOVUPD—Move Unaligned Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#AC(0) If alig

Vol. 2A 3-689INSTRUCTION SET REFERENCE, A-MMOVUPD—Move Unaligned Packed Double-Precision Floating-Point Values#UD If CR0.EM[bit 2] = 1.If CR4.OSFXSR[

3-690 Vol. 2A MOVUPS—Move Unaligned Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MMOVUPS—Move Unaligned Packed Single-Pre

Vol. 2A 3-691INSTRUCTION SET REFERENCE, A-MMOVUPS—Move Unaligned Packed Single-Precision Floating-Point ValuesProtected Mode Exceptions#AC(0) If align

3-692 Vol. 2A MOVUPS—Move Unaligned Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#UD If CR0.EM[bit 2] = 1.If CR4.OSFXSR

Vol. 2A 3-693INSTRUCTION SET REFERENCE, A-MMOVZX—Move with Zero-ExtendMOVZX—Move with Zero-ExtendDescriptionCopies the contents of the source operand

3-28 Vol. 2A ADC—Add with CarryINSTRUCTION SET REFERENCE, A-MDescriptionAdds the destination operand (first operand), the source operand (second opera

3-694 Vol. 2A MOVZX—Move with Zero-ExtendINSTRUCTION SET REFERENCE, A-M#SS(0) If a memory operand effective address is outside the SS segment limit.#P

Vol. 2A 3-695INSTRUCTION SET REFERENCE, A-MMUL—Unsigned MultiplyMUL—Unsigned MultiplyDescriptionPerforms an unsigned multiplication of the first opera

3-696 Vol. 2A MUL—Unsigned MultiplyINSTRUCTION SET REFERENCE, A-MOperationIF (Byte operation)THEN AX ← AL ∗ SRC;ELSE (* Word or doubleword operation *

Vol. 2A 3-697INSTRUCTION SET REFERENCE, A-MMUL—Unsigned Multiply#SS(0) If a memory operand effective address is outside the SS segment limit.#PF(fault

3-698 Vol. 2A MULPD—Multiply Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MMULPD—Multiply Packed Double-Precision Floatin

Vol. 2A 3-699INSTRUCTION SET REFERENCE, A-MMULPD—Multiply Packed Double-Precision Floating-Point Values#UD If an unmasked SIMD floating-point excepti

3-700 Vol. 2A MULPD—Multiply Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#UD If an unmasked SIMD floating-point except

Vol. 2A 3-701INSTRUCTION SET REFERENCE, A-MMULPS—Multiply Packed Single-Precision Floating-Point ValuesMULPS—Multiply Packed Single-Precision Floating

3-702 Vol. 2A MULPS—Multiply Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#XM If an unmasked SIMD floating-point except

Vol. 2A 3-703INSTRUCTION SET REFERENCE, A-MMULPS—Multiply Packed Single-Precision Floating-Point Values#XM If an unmasked SIMD floating-point excepti

Vol. 2A 3-29INSTRUCTION SET REFERENCE, A-MADC—Add with CarryIf the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment

3-704 Vol. 2A MULSD—Multiply Scalar Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MMULSD—Multiply Scalar Double-Precision Floatin

Vol. 2A 3-705INSTRUCTION SET REFERENCE, A-MMULSD—Multiply Scalar Double-Precision Floating-Point Values#UD If an unmasked SIMD floating-point excepti

3-706 Vol. 2A MULSD—Multiply Scalar Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#UD If an unmasked SIMD floating-point except

Vol. 2A 3-707INSTRUCTION SET REFERENCE, A-MMULSS—Multiply Scalar Single-Precision Floating-Point ValuesMULSS—Multiply Scalar Single-Precision Floating

3-708 Vol. 2A MULSS—Multiply Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#UD If an unmasked SIMD floating-point except

Vol. 2A 3-709INSTRUCTION SET REFERENCE, A-MMULSS—Multiply Scalar Single-Precision Floating-Point Values#UD If an unmasked SIMD floating-point excepti

3-710 Vol. 2A MWAIT—Monitor WaitINSTRUCTION SET REFERENCE, A-MMWAIT—Monitor WaitDescriptionMWAIT instruction provides hints to allow the processor to

Vol. 2A 3-711INSTRUCTION SET REFERENCE, A-MMWAIT—Monitor Waitprocessor will exit the state and handle the interrupt. If an SMI caused the processor to

3-712 Vol. 2A MWAIT—Monitor WaitINSTRUCTION SET REFERENCE, A-MNote that if MWAIT is used to enter any of the C-states that are numerically higher than

Vol. 2A 3-713INSTRUCTION SET REFERENCE, A-MMWAIT—Monitor WaitEDX = 0 (* Hints *)IF ( !trigger_store_happened) {MONITOR EAX, ECX, EDXIF ( !trigger_stor

3-30 Vol. 2A ADD—AddINSTRUCTION SET REFERENCE, A-MADD—AddOpcode Instruction 64-Bit Mode Compat/Leg ModeDescription04 ib ADD AL, imm8 Valid Valid Add i

3-714 Vol. 2A MWAIT—Monitor WaitINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions

Vol. 2A 3-31INSTRUCTION SET REFERENCE, A-MADD—AddDescriptionAdds the destination operand (first operand) and the source operand (second operand) and t

3-32 Vol. 2A ADD—AddINSTRUCTION SET REFERENCE, A-M#SS If a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is

Vol. 2A 3-33INSTRUCTION SET REFERENCE, A-MADDPD—Add Packed Double-Precision Floating-Point ValuesADDPD—Add Packed Double-Precision Floating-Point Valu

CONTENTSviiiVol. 2APAGEJMP—Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-34 Vol. 2A ADDPD—Add Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#UD If an unmasked SIMD floating-point exception an

Vol. 2A 3-35INSTRUCTION SET REFERENCE, A-MADDPD—Add Packed Double-Precision Floating-Point Values#UD If an unmasked SIMD floating-point exception and

3-36 Vol. 2A ADDPS—Add Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MADDPS—Add Packed Single-Precision Floating-Point Val

Vol. 2A 3-37INSTRUCTION SET REFERENCE, A-MADDPS—Add Packed Single-Precision Floating-Point Values#XM If an unmasked SIMD floating-point exception and

3-38 Vol. 2A ADDPS—Add Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#XM If an unmasked SIMD floating-point exception an

Vol. 2A 3-39INSTRUCTION SET REFERENCE, A-MADDSD—Add Scalar Double-Precision Floating-Point ValuesADDSD—Add Scalar Double-Precision Floating-Point Valu

3-40 Vol. 2A ADDSD—Add Scalar Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#UD If an unmasked SIMD floating-point exception an

Vol. 2A 3-41INSTRUCTION SET REFERENCE, A-MADDSD—Add Scalar Double-Precision Floating-Point Values#UD If an unmasked SIMD floating-point exception and

3-42 Vol. 2A ADDSS—Add Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MADDSS—Add Scalar Single-Precision Floating-Point Val

Vol. 2A 3-43INSTRUCTION SET REFERENCE, A-MADDSS—Add Scalar Single-Precision Floating-Point Values#UD If an unmasked SIMD floating-point exception and

Vol. 2A ixCONTENTSPAGEMOVNTDQ—Store Double Quadword Using Non-Temporal Hint . . . . . . . . . . . . . . . . . 3-649MOVNTI—Store Doubleword Using Non-

3-44 Vol. 2A ADDSS—Add Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#UD If an unmasked SIMD floating-point exception an

Vol. 2A 3-45INSTRUCTION SET REFERENCE, A-MADDSUBPD—Packed Double-FP Add/SubtractADDSUBPD—Packed Double-FP Add/SubtractDescriptionAdds the double-preci

3-46 Vol. 2A ADDSUBPD—Packed Double-FP Add/SubtractINSTRUCTION SET REFERENCE, A-MOperationxmm1[63:0] = xmm1[63:0] − xmm2/m128[63:0];xmm1[127:64] = xmm

Vol. 2A 3-47INSTRUCTION SET REFERENCE, A-MADDSUBPD—Packed Double-FP Add/Subtract#UD If CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions num

3-48 Vol. 2A ADDSUBPD—Packed Double-FP Add/SubtractINSTRUCTION SET REFERENCE, A-M#UD If an unmasked SIMD floating-point exception and CR4.OSXM-MEXCPT

Vol. 2A 3-49INSTRUCTION SET REFERENCE, A-MADDSUBPS—Packed Single-FP Add/SubtractADDSUBPS—Packed Single-FP Add/SubtractDescriptionAdds odd-numbered sin

3-50 Vol. 2A ADDSUBPS—Packed Single-FP Add/SubtractINSTRUCTION SET REFERENCE, A-MOperationxmm1[31:0] = xmm1[31:0] − xmm2/m128[31:0];xmm1[63:32] = xmm1

Vol. 2A 3-51INSTRUCTION SET REFERENCE, A-MADDSUBPS—Packed Single-FP Add/Subtract#XM For an unmasked Streaming SIMD Extensions numeric excep-tion, CR4

3-52 Vol. 2A ADDSUBPS—Packed Single-FP Add/SubtractINSTRUCTION SET REFERENCE, A-M#UD If an unmasked SIMD floating-point exception and CR4.OSXM-MEXCPT

Vol. 2A 3-53INSTRUCTION SET REFERENCE, A-MAND—Logical ANDAND—Logical ANDOpcode Instruction 64-Bit ModeComp/Leg ModeDescription24 ib AND AL, imm8 Valid