Intel BX80569QX6850 Scheda Tecnica

Document Number: 313278-007Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ and E4000Δ Sequences Datasheet—on 65

10 Datasheet§ §

Features100 Datasheet

Datasheet 101Boxed Processor Specifications7 Boxed Processor SpecificationsThe processor is also offered as an Intel boxed processor. Intel boxed proc

Boxed Processor Specifications102 Datasheet7.1 Mechanical Specifications7.1.1 Boxed Processor Cooling Solution DimensionsThis section documents the me

Datasheet 103Boxed Processor Specifications7.1.2 Boxed Processor Fan Heatsink WeightThe boxed processor fan heatsink will not weigh more than 550 gram

Boxed Processor Specifications104 DatasheetThe boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and does not support va

Datasheet 105Boxed Processor Specifications7.3 Thermal SpecificationsThis section describes the cooling requirements of the fan heatsink solution used

Boxed Processor Specifications106 Datasheet Figure 37. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)Figure 38. Boxed Proces

Datasheet 107Boxed Processor Specifications7.3.2 Fan Speed Control Operation (Intel® Core2 Extreme Processor X6800 Only)The boxed processor fan heatsi

Boxed Processor Specifications108 DatasheetNOTES:1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.If the boxed processo

Datasheet 109Boxed Processor SpecificationsIf the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan heade

Datasheet 11Introduction1 IntroductionThe Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and E4000 sequences comb

Boxed Processor Specifications110 Datasheet

Datasheet 111Balanced Technology Extended (BTX) Boxed Processor Specifications8 Balanced Technology Extended (BTX) Boxed Processor SpecificationsThe p

Balanced Technology Extended (BTX) Boxed Processor Specifications112 DatasheetNOTE: The duct, clip, heatsink and fan can differ from this drawing repr

Datasheet 113Balanced Technology Extended (BTX) Boxed Processor SpecificationsNOTE: Diagram does not show the attached hardware for the clip design an

Balanced Technology Extended (BTX) Boxed Processor Specifications114 DatasheetNOTE: Diagram does not show the attached hardware for the clip design an

Datasheet 115Balanced Technology Extended (BTX) Boxed Processor Specifications8.1.3 Boxed Processor Support and Retention Module (SRM)The boxed proces

Balanced Technology Extended (BTX) Boxed Processor Specifications116 Datasheet8.2 Electrical Requirements8.2.1 Thermal Module Assembly Power SupplyThe

Datasheet 117Balanced Technology Extended (BTX) Boxed Processor SpecificationsTable 40. TMA Power and Signal SpecificationsDescription Min Typ Max Uni

Balanced Technology Extended (BTX) Boxed Processor Specifications118 Datasheet8.3 Thermal SpecificationsThis section describes the cooling requirement

Datasheet 119Balanced Technology Extended (BTX) Boxed Processor SpecificationsNOTES:1. Set point variance is approximately ±1°C from Thermal Module As

Introduction12 Datasheet1.1 TerminologyA ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state whe

Balanced Technology Extended (BTX) Boxed Processor Specifications120 Datasheetthe motherboard that sends out a PWM control signal to the 4th pin of th

Datasheet 121Debug Tools Specifications9 Debug Tools Specifications9.1 Logic Analyzer Interface (LAI)Intel is working with two logic analyzer vendors

Debug Tools Specifications122 Datasheet

Datasheet 13Introduction• Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system

Introduction14 Datasheet1.2 ReferencesMaterial and concepts available in the following documents may be beneficial when reading this document.§ §Table

Datasheet 15Electrical Specifications2 Electrical SpecificationsThis chapter describes the electrical characteristics of the processor interfaces and

Electrical Specifications16 Datasheet2.2.3 FSB DecouplingThe processor integrates signal termination on the die. In addition, some of the high frequen

Datasheet 17Electrical SpecificationsTable 2. Voltage Identification DefinitionVID6 VID5 VID4 VID3 VID2 VID1 VID (V) VID6 VID5 VID4 VID3 VID2 VID1 VID

Electrical Specifications18 Datasheet2.4 Market Segment Identification (MSID)The MSID[1:0] signals may be used as outputs to determine the Market Segm

Datasheet 19Electrical SpecificationsThe TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resis

2 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO AN

Electrical Specifications20 Datasheet2.6.2 DC Voltage and Current SpecificationTable 4. Absolute Maximum and Minimum RatingsSymbol Parameter Min Max U

Datasheet 21Electrical SpecificationsICCProcessor NumberE6850E6750E6700E6600E6550E6540 E6400/E6420E6300/E6320E4600E4500E4400E4300ICC for 775_VR_CONFIG

Electrical Specifications22 DatasheetTable 6. VCC Static and Transient Tolerance for Processors with 4 MB L2 CacheICC (A)Voltage Deviation from VID Se

Datasheet 23Electrical SpecificationsNOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as sho

Electrical Specifications24 DatasheetTable 7. VCC Static and Transient Tolerance for Processors with 2 MB L2 CacheICC (A)Voltage Deviation from VID Se

Datasheet 25Electrical SpecificationsNOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as sho

Electrical Specifications26 DatasheetNOTES:1. VOS is measured overshoot voltage.2. TOS is measured time duration above VID.2.6.4 Die Voltage Validatio

Datasheet 27Electrical Specifications2.7.1 FSB Signal GroupsThe front side bus signals have been combined into groups by buffer type. GTL+ input signa

Electrical Specifications28 Datasheet.. 2.7.2 CMOS and Open Drain SignalsLegacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS

Datasheet 29Electrical Specifications2.7.3 Processor DC SpecificationsThe processor DC specifications in this section are defined at the processor cor

Datasheet 3Contents1Introduction...111.1 Term

Electrical Specifications30 Datasheet.2.7.3.1 GTL+ Front Side Bus SpecificationsIn most cases, termination resistors are not required as these are int

Datasheet 31Electrical Specifications2.7.4 Clock Specifications2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor ClockingBCLK[1:0] directly control

Electrical Specifications32 Datasheet2.7.7 Phase Lock Loop (PLL) and FilterAn on-die PLL filter solution will be implemented on the processor. The VCC

Datasheet 33Electrical SpecificationsFigure 4. Differential Clock WaveformFigure 5. Differential Clock Crosspoint SpecificationFigure 6. Differential

Electrical Specifications34 Datasheet2.7.9 BCLK[1:0] Specifications (CK410 based Platforms)Table 19. Front Side Bus Differential BCLK SpecificationsSy

Datasheet 35Electrical Specifications2.8 PECI DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel

Electrical Specifications36 Datasheet

Datasheet 37Package Mechanical Specifications3 Package Mechanical SpecificationsThe processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) pac

Package Mechanical Specifications38 DatasheetFigure 9. Processor Package Drawing Sheet 1 of 3

Datasheet 39Package Mechanical SpecificationsFigure 10. Processor Package Drawing Sheet 2 of 3

4 Datasheet5.2.5 THERMTRIP# Signal...895.3 Thermal Diode...

Package Mechanical Specifications40 DatasheetFigure 11. Processor Package Drawing Sheet 3 of 3

Datasheet 41Package Mechanical Specifications3.1.1 Processor Component Keep-Out ZonesThe processor may contain components on the substrate that define

Package Mechanical Specifications42 Datasheet3.1.4 Package Insertion SpecificationsThe processor can be inserted into and removed from a LGA775 socket

Datasheet 43Package Mechanical SpecificationsFigure 13. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequenc

Package Mechanical Specifications44 DatasheetEEFigure 15. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E4000 Seque

Datasheet 45Package Mechanical Specifications3.1.8 Processor Land CoordinatesFigure 17 shows the top view of the processor land coordinates. The coord

Package Mechanical Specifications46 Datasheet

Datasheet 47Land Listing and Signal Descriptions4 Land Listing and Signal DescriptionsThis chapter provides the processor land assignment and signal d

Land Listing and Signal Descriptions48 DatasheetFigure 18. land-out Diagram (Top View – Left Side)30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15ANVCC

Datasheet 49Land Listing and Signal DescriptionsFigure 19. land-out Diagram (Top View – Right Side)14 13 12 11 10 9 8 7 6 5 4 3 2 1VCC VSS VCC VCC VSS

Datasheet 5Figures1VCC Static and Transient Tolerance for Processors with 4 MB L2 Cache ...232VCC Static and Transient Tolera

Land Listing and Signal Descriptions50 DatasheetTable 24. Alphabetical Land AssignmentsLand NameLand #Signal Buffer TypeDirectionA3# L5 Source Synch I

Land Listing and Signal DescriptionsDatasheet 51D22# D10 Source Synch Input/OutputD23# F11 Source Synch Input/OutputD24# F12 Source Synch Input/Output

Land Listing and Signal Descriptions52 DatasheetFC33 H16 Power/OtherFC34 J17 Power/OtherFC35 H4 Power/OtherFC36 AD3 Power/OtherFC37 AB3 Power/OtherFC3

Land Listing and Signal DescriptionsDatasheet 53TRDY# E3 Common Clock InputTRST# AG1 TAP InputVCC AA8 Power/Other VCC AB8 Power/Other VCC AC23 Power

Land Listing and Signal Descriptions54 DatasheetVCC AJ18 Power/Other VCC AJ19 Power/Other VCC AJ21 Power/Other VCC AJ22 Power/Other VCC AJ25 Power

Land Listing and Signal DescriptionsDatasheet 55VCC J28 Power/Other VCC J29 Power/Other VCC J30 Power/Other VCC J8 Power/Other VCC J9 Power/Other

Land Listing and Signal Descriptions56 DatasheetVID0 AM2 Power/Other OutputVID1 AL5 Power/Other OutputVID2 AM3 Power/Other OutputVID3 AL6 Power/Other

Land Listing and Signal DescriptionsDatasheet 57VSS AG23 Power/Other VSS AG24 Power/Other VSS AG7 Power/Other VSS AH1 Power/Other VSS AH10 Power/O

Land Listing and Signal Descriptions58 DatasheetVSS B24 Power/Other VSS B5 Power/Other VSS B8 Power/Other VSS C10 Power/Other VSS C13 Power/Other

Land Listing and Signal DescriptionsDatasheet 59VSS N6 Power/Other VSS N7 Power/Other VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other

6 DatasheetTables1 Reference Documents ...142 Voltage Iden

Land Listing and Signal Descriptions60 DatasheetTable 25. Numerical Land AssignmentLand #Land NameSignal Buffer TypeDirectionA2 VSS Power/Other A3 RS

Land Listing and Signal DescriptionsDatasheet 61C20 DBI3# Source Synch Input/OutputC21 D58# Source Synch Input/OutputC22 VSS Power/Other C23 VCCIOPLL

Land Listing and Signal Descriptions62 DatasheetF11 D23# Source Synch Input/OutputF12 D24# Source Synch Input/OutputF13 VSS Power/Other F14 D28# Sour

Land Listing and Signal DescriptionsDatasheet 63H30 BSEL1 Power/Other OutputJ1 VTT_OUT_LEFT Power/Other OutputJ2 FC3 Power/OtherJ3 FC22 Power/Other J

Land Listing and Signal Descriptions64 DatasheetM30 VCC Power/Other N1 PWRGOOD Power/Other InputN2 IGNNE# Asynch CMOS InputN3 VSS Power/Other N4 RES

Land Listing and Signal DescriptionsDatasheet 65U28 VCC Power/Other U29 VCC Power/OtherU30 VCC Power/Other V1 MSID1 Power/Other OutputV2 RESERVEDV3

Land Listing and Signal Descriptions66 DatasheetAB26 VSS Power/Other AB27 VSS Power/Other AB28 VSS Power/Other AB29 VSS Power/Other AB30 VSS Power

Land Listing and Signal DescriptionsDatasheet 67AF12 VCC Power/Other AF13 VSS Power/Other AF14 VCC Power/Other AF15 VCC Power/Other AF16 VSS Power

Land Listing and Signal Descriptions68 DatasheetAH30 VCC Power/Other AJ1 BPM1# Common Clock Input/OutputAJ2 BPM0# Common Clock Input/OutputAJ3 ITP_CL

Land Listing and Signal DescriptionsDatasheet 69AL18 VCC Power/Other AL19 VCC Power/Other AL20 VSS Power/Other AL21 VCC Power/Other AL22 VCC Power

Datasheet 7Revision HistoryRevision NumberDescription Date-001 • Initial release July 2006-002 • Corrected L1 Cache information September 2006-003•Add

Land Listing and Signal Descriptions70 Datasheet4.2 Alphabetical Signals ReferenceTable 26. Signal Description (Sheet 1 of 9)Name Type DescriptionA[35

Land Listing and Signal DescriptionsDatasheet 71BPM[5:0]#Input/OutputBPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. Th

Land Listing and Signal Descriptions72 DatasheetD[63:0]#Input/OutputD[63:0]# (Data) are the data signals. These signals provide a 64-bit data path bet

Land Listing and Signal DescriptionsDatasheet 73DEFER# InputDEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order c

Land Listing and Signal Descriptions74 DatasheetHIT#HITM#Input/OutputInput/OutputHIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop op

Land Listing and Signal DescriptionsDatasheet 75LOCK#Input/OutputLOCK# indicates to the system that a transaction must occur atomically. This signal m

Land Listing and Signal Descriptions76 DatasheetRESERVEDAll RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to

Datasheet 77Land Listing and Signal DescriptionsTHERMTRIP# OutputIn the event of a catastrophic cooling failure, the processor will automatically shut

Land Listing and Signal Descriptions78 Datasheet§ §VRDSEL InputThis input should be left as a no connect in order for the processor to boot. The proce

Datasheet 79Thermal Specifications and Design Considerations5 Thermal Specifications and Design Considerations5.1 Processor Thermal SpecificationsThe

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Thermal Specifications and Design Considerations80 DatasheetThe case temperature is defined at the geometric top center of the processor. Analysis ind

Datasheet 81Thermal Specifications and Design ConsiderationsTable 28. Thermal Profile (Intel® Core™2 Duo Desktop Processor E6x50 Sequence and E6540 wi

Thermal Specifications and Design Considerations82 DatasheetTable 29. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 Sequence with 4 MB L2

Datasheet 83Thermal Specifications and Design ConsiderationsTable 30. Thermal Profile (Intel® Core™2 Duo Desktop Processor E4500 and E4600 with 2 MB L

Thermal Specifications and Design Considerations84 DatasheetTable 31. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 and E4000 Sequence wit

Datasheet 85Thermal Specifications and Design ConsiderationsTable 32. Thermal Profile (Intel® Core™2 Extreme Processor X6800)Power (W)Maximum Tc (°C)P

Thermal Specifications and Design Considerations86 Datasheet5.1.2 Thermal MetrologyThe maximum and minimum case temperatures (TC) for the processor is

Datasheet 87Thermal Specifications and Design Considerationsand in some cases may result in a TC that exceeds the specified maximum temperature and ma

Thermal Specifications and Design Considerations88 DatasheetThe PROCHOT# signal is asserted when a high temperature situation is detected, regardless

Datasheet 89Thermal Specifications and Design Considerations5.2.4 PROCHOT# SignalAn external signal, PROCHOT# (processor hot), is asserted when the pr

Datasheet 9Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Features The Intel Core™2 Extreme pr

Thermal Specifications and Design Considerations90 Datasheet5.3 Thermal DiodeThe processor incorporates an on-die PNP transistor where the base emitte

Datasheet 91Thermal Specifications and Design ConsiderationsNOTES:1. Intel does not support or recommend operation of the thermal diode under reverse

Thermal Specifications and Design Considerations92 Datasheet5.4 Platform Environment Control Interface (PECI)5.4.1 IntroductionPECI offers an interfac

Datasheet 93Thermal Specifications and Design Considerations..Figure 28. Conceptual Fan Control on PECI-Based PlatformsMinMaxFan Speed(RPM)TCONTROLSet

Thermal Specifications and Design Considerations94 Datasheet5.4.2 PECI Specifications5.4.2.1 PECI Device AddressThe PECI device address for the socket

Datasheet 95Features6 Features6.1 Power-On Configuration OptionsSeveral configuration options can be configured by hardware. The processor samples the

Features96 Datasheet6.2.1 Normal StateThis is the normal operating state for the processor.6.2.2 HALT and Extended HALT Powerdown StatesThe processor

Datasheet 97FeaturesThe system can generate a STPCLK# while the processor is in the HALT powerdown state. When the system de-asserts the STPCLK# inter

Features98 Datasheet6.2.3.2 Extended Stop Grant State Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted and Extende

Datasheet 99Featurespoints. It alters the performance of the processor by changing the bus to core frequency ratio and voltage. This allows the proces