Intel SR1500NA Scheda Tecnica Pagina 60

  • Scaricare
  • Aggiungi ai miei manuali
  • Stampa
  • Pagina
    / 104
  • Indice
  • SEGNALIBRI
  • Valutato. / 5. Basato su recensioni clienti
Vedere la pagina 59
Intel® Server System SR1550AL Peripheral and Hard Drive Sub-System
Revision – 1.3
Intel order number D31982-006
47
6.4.2 SAS/SATA Backplane Functional Architecture
The figure below shows the functional blocks of the SAS/SATA backplane.
Figure 33. SAS/SATA Backplane Functional Block Diagram
6.4.2.1 Enclosure Management Controller
The backplane utilizes the features of the Vitesse* VSC410 to implement several enclosure
management functions. The chip provides in-band SAF-TE and SES management and utilizes
four I
2
C interfaces.
1. I2C bus 0 is connected to an EEPROM which stores configuration and FRU data
2. I2C bus 1 is connected to an LM75 temperature sensor
3. I2C bus 2 is connected to an IPMB bus from the server board.
4. I2C bus 3 is connected to the LSISAS1068 SAS controller.
Vedere la pagina 59
1 2 ... 55 56 57 58 59 60 61 62 63 64 65 ... 103 104

Commenti su questo manuale

Nessun commento