Intel 440GX Manuale Utente

Intel® 440GX AGPsetDesign GuideMarch 1999Order Number: 290651-001

xIntel® 440GX AGPset Design Guide

Intel® 440GX AGPset Design Guide4-1Debug RecommendationsDebug Recommendations4This chapter provides tool information, logic suggestions, technical sup

Intel® 440GX AGPset Design Guide4-2Debug RecommendationsContact your local Intel Field Sales representative to complete the proper software license ag

Intel® 440GX AGPset Design Guide4-3Debug RecommendationsThe extra loading of the LAI562 requires stronger pull-up values on the target system. However

Intel® 440GX AGPset Design Guide4-4Debug RecommendationsInputs to the Slot 1 connector, from system logic (assuming a 14mA driver):•PWRGOOD 150 - 330

Intel® 440GX AGPset Design Guide4-5Debug Recommendations4.3.2.1 Debug Considerations•As technology drives better low power modes, the VccCORE current

Intel® 440GX AGPset Design Guide4-6Debug Recommendations•The Global Descriptor Table (GDT) must be aligned. The GDT must be located on a DWord boundar

5Third Party Vendors

Intel® 440GX AGPset Design Guide5-1Third-Party Vendor InformationThird-Party Vendor Information5This design guide has been compiled to give an overvie

1Introduction

Intel® 440GX AGPset Design Guide5-2Third-Party Vendor Information5.1.1 Voltage Regulator ModulesThe following vendors are developing DC-DC converter m

Intel® 440GX AGPset Design Guide5-3Third-Party Vendor Information5.2 Intel® 440GX AGPset5.2.1 Clock DriversIntel has supplied specifications to clock

Third-Party Vendor Information5-4Intel® 440GX AGPset Design Guide5.3 Other Processor Components 5.3.1 Slot 1 ConnectorPublic information; see Intel® P

AReference Design Schematics

Intel® 440GX AGPset Design GuideA-1Intel® 440GX AGPset Platform Reference DesignIntel® 440GX AGPset Platform Reference Design AThis section describes

Intel® 440GX AGPset Platform Reference DesignA-2Intel® 440GX AGPset Design Guide82443GX Component (System bus and DRAM Interfaces) 8This page shows th

Intel® 440GX AGPset Design GuideA-3Intel® 440GX AGPset Platform Reference DesignUltra I/O Component 20This page shows the Ultra I/O component. The RTC

Intel® 440GX AGPset Platform Reference DesignA-4Intel® 440GX AGPset Design GuidePower Connectors Front Panel Jumpers 32This page shows the system ATX

Intel® 440GX AGPset Design Guide1-1IntroductionIntroduction1This document provides design guidelines for developing Intel® Pentium® II processor / Int

Intel® 440GX AGPset Design Guide1-2Introduction1.2 References•Intel® Pentium® II Processor Datasheet•Intel® 440GX AGPset Datasheet (WWW; order number

Intel® 440GX AGPset Design Guide1-3Introduction1.3 Intel® Pentium® II Processor / Intel® 440GX AGPset OverviewThe following is a list of features that

Intel® 440GX AGPset Design Guide1-4IntroductionIntel introduced the Intel® Pentium® II processor as 350/100 and 400/100 speeds with 512 KB L2 cache ve

Intel® 440GX AGPset Design Guide1-5IntroductionFigure 1-1 shows a block diagram of a typical platform based on the Intel® 440GX AGPset. The 82443GX sy

Intel® 440GX AGPset Design Guide1-6Introduction1.3.2.4 PCI InterfaceThe 82443GX PCI interface is 33 MHz Revision 2.1 compliant and supports up to five

Intel® 440GX AGPset Design Guide1-7IntroductionManageability features in each of these four technology areas combine to form the Wired for Management

Intel® 440GX AGPset Design GuideInformation in this document is provided in connection with Intel products. No license, express or implied, by estoppe

Intel® 440GX AGPset Design Guide1-8Introduction1.3.3.3 Remote Wake-UpIf a PC supports a reduced power state, it must be possible to bring the system t

Intel® 440GX AGPset Design Guide1-9Introduction1.4.2 General Design Recommendations1. Intel recommends using an industry standard programmable Voltage

Introduction1-10Intel® 440GX AGPset Design Guide

2Motherboard Design

Intel® 440GX AGPset Design Guide2-1Motherboard Layout and Routing GuidelinesMotherboard Layout and Routing Guidelines2This chapter describes layout an

Motherboard Layout and Routing Guidelines2-2Intel® 440GX AGPset Design GuideFigure 2-2 and Figure 2-3 show the proposed component placement for a sing

Intel® 440GX AGPset Design Guide2-3Motherboard Layout and Routing GuidelinesNLX Form Factor:1. The NLX placement and layout below is recommended for a

Motherboard Layout and Routing Guidelines2-4Intel® 440GX AGPset Design GuideNote: The top and bottom routing layers specify 1/2 oz. cu. However, by th

Intel® 440GX AGPset Design Guide2-5Motherboard Layout and Routing GuidelinesAdditional guidelines on board buildup, placement and layout include:•For

Intel® 440GX AGPset Design GuideiiiContents1 Introduction ...

Motherboard Layout and Routing Guidelines2-6Intel® 440GX AGPset Design Guide2.3.1 GTL+ DescriptionGTL+ is the electrical bus technology used for the I

Intel® 440GX AGPset Design Guide2-7Motherboard Layout and Routing Guidelines2.3.3.2 Single Processor Recommended Trace LengthsSingle processor trace l

Motherboard Layout and Routing Guidelines2-8Intel® 440GX AGPset Design Guide2.3.4 Dual Processor Systems2.3.4.1 Dual Processor Network Topology and Co

Intel® 440GX AGPset Design Guide2-9Motherboard Layout and Routing GuidelinesIn the SET topology, the only termination is on the Intel® Pentium® II pro

Motherboard Layout and Routing Guidelines2-10Intel® 440GX AGPset Design Guide2.3.6 Additional Guidelines2.3.6.1 Minimizing CrosstalkThe following gene

Intel® 440GX AGPset Design Guide2-11Motherboard Layout and Routing Guidelines2.3.7 Design Methodology Intel recommends using the following design meth

Motherboard Layout and Routing Guidelines2-12Intel® 440GX AGPset Design Guide2.3.8 Performance RequirementsPrior to performing interconnect simulation

Intel® 440GX AGPset Design Guide2-13Motherboard Layout and Routing GuidelinesSection 2.7, “Timing Analysis” on page 2-17 describes the timing analysis

Motherboard Layout and Routing Guidelines2-14Intel® 440GX AGPset Design GuideThe methodology that Intel recommends is known as “Sensitivity Analysis”.

Intel® 440GX AGPset Design Guide2-15Motherboard Layout and Routing Guidelines2.5.1 Crosstalk and the Multi-Bit Adjustment FactorCoupled lines should b

ivIntel® 440GX AGPset Design Guide2.6 Validation ...2

Motherboard Layout and Routing Guidelines2-16Intel® 440GX AGPset Design Guide2.6.2 Signal Quality MeasurementSignal integrity is specified at the proc

Intel® 440GX AGPset Design Guide2-17Motherboard Layout and Routing Guidelines2.7 Timing AnalysisTo determine the available flight time window perform

Motherboard Layout and Routing Guidelines2-18Intel® 440GX AGPset Design GuideNotice that the timing equations include an extra term to account for the

Intel® 440GX AGPset Design Guide2-19Motherboard Layout and Routing Guidelines2.8 AGP Layout and Routing GuidelinesFor the definition of AGP Interface

Motherboard Layout and Routing Guidelines2-20Intel® 440GX AGPset Design GuideIt is always best to reduce the line length mismatch wherever possible to

Intel® 440GX AGPset Design Guide2-21Motherboard Layout and Routing GuidelinesFor trace lengths that are between 1.0 inch and 4.5 inches, a 1:1 trace s

Motherboard Layout and Routing Guidelines2-22Intel® 440GX AGPset Design GuideSome of the control signals require pull-up resistors to be installed on

Intel® 440GX AGPset Design Guide2-23Motherboard Layout and Routing GuidelinesThere are also “population” rules which need to be observed. To properly

Motherboard Layout and Routing Guidelines2-24Intel® 440GX AGPset Design Guide2.9.1.3 Trace Width vs. Trace SpacingTo minimize the crosstalk, a 1:2 tra

Intel® 440GX AGPset Design Guide2-25Motherboard Layout and Routing Guidelines.Table 2-18. FET Switch DQ Route ExampleFigure 2-20. Motherboard Model—Da

Intel® 440GX AGPset Design Guidev3.7 82371EB (PIIX4E)...3-163.7.1

Motherboard Layout and Routing Guidelines2-26Intel® 440GX AGPset Design GuideFigure 2-21. Motherboard Model—DQMA[0,2:4,6:7], 4 DIMMsFigure 2-22. Mothe

Intel® 440GX AGPset Design Guide2-27Motherboard Layout and Routing GuidelinesFigure 2-24. Motherboard Model—DQM_B[1,5], 4 DIMMs82443GX1.0” - 3.25”0.4”

Motherboard Layout and Routing Guidelines2-28Intel® 440GX AGPset Design GuideTable 2-19. Motherboard Model: SRAS_B#, 4 DIMMsTable 2-20. Motherboard Mo

Intel® 440GX AGPset Design Guide2-29Motherboard Layout and Routing GuidelinesTable 2-22. Motherboard Model: WE_A#, 4 DIMMsTable 2-23. Motherboard Mode

Motherboard Layout and Routing Guidelines2-30Intel® 440GX AGPset Design Guide2.9.3 4 DIMM Routing Guidelines [NO FET]2.9.4 PCI Bus Routing GuidelinesT

Intel® 440GX AGPset Design Guide2-31Motherboard Layout and Routing GuidelinesBecause of the specifics of an ATX layout, it is recommended that the PII

Motherboard Layout and Routing Guidelines2-32Intel® 440GX AGPset Design Guide2.9.6 Intel® 440GX AGPset Clock Layout Recommendations2.9.6.1 Clock Routi

Intel® 440GX AGPset Design Guide2-33Motherboard Layout and Routing Guidelines2.9.6.3 PCI Clock LayoutPCI clock nets should be routed a point-to-point

Motherboard Layout and Routing Guidelines2-34Intel® 440GX AGPset Design Guide2.9.6.5 AGP Clock LayoutSeries Termination: 22 Ohm series termination sho

3Design Checklist

viIntel® 440GX AGPset Design Guide4.3 Debug Features ...4-24.

Intel® 440GX AGPset Design Guide3-1Design ChecklistDesign Checklist33.1 OverviewThe following checklist is intended to be used for schematic reviews o

Intel® 440GX AGPset Design Guide3-2Design Checklist3.3 Intel® Pentium® II Processor Checklist3.3.1 Intel® Pentium® II ProcessorFigure 3-1. Pull-up Res

Intel® 440GX AGPset Design Guide3-3Design ChecklistDBSY#UP: Connect to 82443GX; DP: Connect CPUs and 82443GX.DEFER#UP: Connect to 82443GX; DP: Connect

Intel® 440GX AGPset Design Guide3-4Design ChecklistTDOUP: Connected to ITP. 150 ohm pull-up to 2.5V.DP: Connected to jumpers between ITP and CPU signa

Intel® 440GX AGPset Design Guide3-5Design Checklist3.3.2 Intel® Pentium® II Processor Clocks•Include a circuit for the system bus clock to core freque

Intel® 440GX AGPset Design Guide3-6Design Checklistused by other logic requiring CMOS/TTL logic levels. The VID lines on the Slot 1 connector are 5V t

Intel® 440GX AGPset Design Guide3-7Design Checklist3.3.4 Uni-Processor (UP) Slot 1 Checklist •A UP system must connect BREQ0# of the Slot 1 connector

Intel® 440GX AGPset Design Guide3-8Design Checklist3.4 Intel® 440GX AGPset Clocks3.4.1 CK100 - 100 MHz Clock Synthesizer •The system clock which provi

Intel® 440GX AGPset Design Guide3-9Design Checklist3.4.2 CKBF - SDRAM 1 to 18 Clock Buffer •A 4.7K ohm pull-up to VCC3.3 on the OE pin is needed to en

Intel® 440GX AGPset Design GuideviiFigures1-1 Intel® Pentium® II Processor / Intel® 440GX AGPset System Block Diagram...

Intel® 440GX AGPset Design Guide3-10Design Checklist3.5 82443GX Host Bridge3.5.1 82443GX InterfaceTable 3-4. 82443GX Connectivity (Sheet 1 of 3)SIGNAL

Intel® 440GX AGPset Design Guide3-11Design ChecklistGADSTBA, GADSTBB, GDEVSEL#, GFRAME#, GGNT#, GIRDY#, GREQ#, GSTOP#, GTRDY#, 8.2K ohm pull-ups to 3.

Intel® 440GX AGPset Design Guide3-12Design Checklist•GTLREFx pins are driven from independent voltage dividers which set the GTLREFx pins to VTT*2/3 u

Intel® 440GX AGPset Design Guide3-13Design Checklist— TMS (connector pin A3) and TDI (connector pin A4) should be independently bussed and pulled up w

Intel® 440GX AGPset Design Guide3-14Design Checklist3.6 Intel® 440GX AGPset Memory Interface3.6.1 SDRAM ConnectionsNOTES:1. Some of the pin ranges abo

Intel® 440GX AGPset Design Guide3-15Design Checklist3.6.2 DIMM Solution With FET Switches•With existing 64Mbit technology, 512 MB, 1 GB and 2 GB suppo

Intel® 440GX AGPset Design Guide3-16Design Checklist3.7 82371EB (PIIX4E)3.7.1 PIIX4E ConnectionsTable 3-7. PIIX4E Connectivity (Sheet 1 of 4)Signal Na

Intel® 440GX AGPset Design Guide3-17Design ChecklistIOCHCK# Connected to ISA slots. 4.7K ohm pull-up to VCC.IOCHRDY Connected to ISA slots and Ultra I

Intel® 440GX AGPset Design Guide3-18Design ChecklistPHLD# Connected to 82443GX. 8.2K ohm pull-up to VCC3. PHLDA# Connected to 82443GX. 8.2K ohm pull-u

Intel® 440GX AGPset Design Guide3-19Design ChecklistSMBCLK, SMBDATAConnect to all devices on SMBus. 2.7K ohm pull-up to VCC3. This value may need to b

viiiIntel® 440GX AGPset Design GuideTables2-1 Recommended Trace Lengths for Single Processor Design...2-72-2 Recommended Trace Le

Intel® 440GX AGPset Design Guide3-20Design Checklist3.7.2 IDE Routing GuidelinesThis section contains guidelines for connecting and routing the PIIX4E

Intel® 440GX AGPset Design Guide3-21Design ChecklistOne resistor per IDE connector is recommended for all signals. For signals labeled as 22-47Ω, the

Intel® 440GX AGPset Design Guide3-22Design Checklist3.7.3 PIIX4E Power And Ground Pins•Vcc, Vcc(RTC), Vcc(SUS), and Vcc(USB) must be tied to 3.3V.•VRE

Intel® 440GX AGPset Design Guide3-23Design ChecklistThird, if the design currently uses an in-line active gate/buffer on PCIRST# to drive the PCI bus,

Intel® 440GX AGPset Design Guide3-24Design Checklist3.11 USB Interface•Contact your local Intel Field Sales representative for the following Applicati

Intel® 440GX AGPset Design Guide3-25Design Checklist3.13 Flash Design3.13.1 Dual-Footprint Flash DesignNew features are coming to the PC continue to i

Intel® 440GX AGPset Design Guide3-26Design ChecklistFollowing are general layout guidelines for using the Intel’s boot block flash memories (28F001GX/

Intel® 440GX AGPset Design Guide3-27Design Checklist(WP# pin not available on 8-Mbit 44-lead PSOP. In this package, treat as if the WP# pin is interna

Intel® 440GX AGPset Design Guide3-28Design Checklist3.14 System and Test Signals•8.2K ohm pull-up resistor is recommended on the TEST# pin of the PIIX

Intel® 440GX AGPset Design Guide3-29Design Checkliststandby voltage is not provided by the power supply, then tie PWROK signal on the PIIX4E to the RS

Intel® 440GX AGPset Design GuideixRevision HistoryDate Revision Description3/99 -001 Initial Release.

Intel® 440GX AGPset Design Guide3-30Design Checklist•The system reset button has typically been connected indirectly to the PWROK input of the PIIX4/P

Intel® 440GX AGPset Design Guide3-31Design Checklist•Poll the power button status bit during POST while SMIs are not loaded and go directly to soft-of

Intel® 440GX AGPset Design Guide3-32Design Checklistbe stubbed off the trace run and must be as close as possible to the PIIX4/PIIX4E. The capacitor m

Intel® 440GX AGPset Design Guide3-33Design ChecklistPIIX4E. For ACPI compliance, this signal must be connected to the IOAPIC. There are two different

Intel® 440GX AGPset Design Guide3-34Design Checklist•Analog inputs feed inverting op-amp stages, useful for monitoring power supply regulation.•The LM

Intel® 440GX AGPset Design Guide3-35Design Checklist3.18.4 Wake On LAN (WOL) Header•A 3-pin WOL header interconnects the NIC and motherboard, and requ

Intel® 440GX AGPset Design Guide3-36Design Checklist3.19.2 Design Considerations•For UP systems to support both the current Intel® Pentium® II process

Intel® 440GX AGPset Design Guide3-37Design Checklist3.21.1 Design Considerations•The Intel® Pentium® II processor retention mechanism, retention mecha

Intel® 440GX AGPset Design Guide3-38Design Checklist3.23 Layout Checklist3.23.1 Routing and Board Fabrication•VRM 8.2 Support: Is the VccCORE trace/po

4Debug Recommendations