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Electrical Specifications

26 Datasheet

3. The value of these signals during the active-to-inactive edge of RESET# defines the

processor configuration options. See Section 6.1 for details.

4. PROCHOT# signal type is open drain output and CMOS input.

NOTES:

1. Signals that do not have R

, nor are actively driven to their high-voltage level.

NOTE:

1. See Tabl e 1 2 for more information.

2.7.2 CMOS and Open Drain Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS

input buffers. All of the CMOS and Open Drain signals are required to be asserted/de-

asserted for at least eight BCLKs in order for the processor to recognize the proper

signal state. See Section 2.7.3 for the DC specifications. See Section 6.2 for additional

timing requirements for entering and leaving the low power states.

Table 9. Signal Characteristics

Signals with R

Signals with No R

A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,

D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,

DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,

HITM#, LOCK#, PROCHOT#, REQ[4:0]#,

RS[2:0]#, TRDY#

A20M#, BCLK[1:0], BPM[5:0]#, BSEL[2:0],

COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#,

INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/

NMI, MSID[1:0], PWRGOOD, RESET#, SMI#,

STPCLK#, TDO, TESTHI[12,10:0],

THERMTRIP#, VID[7:0], GTLREF[1:0], TCK,

TDI, TMS, TRST#, VTT_SEL

Open Drain Signals

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,

BR0#, TDO, FCx

Table 10. Signal Reference Voltages

GTLREF V

BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,

A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,

DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,

TRDY#

A20M#, LINT0/INTR, LINT1/NMI,

IGNNE#, INIT#, PROCHOT#,

PWRGOOD

, SMI#, STPCLK#, TCK

TDI

, TMS

, TRST#

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 101 102

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