Intel BX80562QX9300 Scheda Tecnica

Document Number: 320390-002Intel® Core™2 Extreme Quad-Core Mobile Processor and Intel® Core™2 Quad Mobile Processor on 45-nm ProcessDatasheetFor platf

Introduction10 Datasheet

Datasheet 11Low Power Features2 Low Power Features2.1 Clock Control and Low Power StatesThe processor supports low power states both at the individual

Low Power Features12 DatasheetFigure 1. Core Low Power States StopGrantC1/MWAITC0C1/AutoHaltHalt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RE

Datasheet 13Low Power FeaturesNOTE:1. AutoHALT or MWAIT/C1.2.1.1 Core Low Power State Descriptions2.1.1.1 Core C0 StateThis is the normal operating st

Low Power Features14 DatasheetWhile in AutoHALT Powerdown state, the due core processor will process bus snoops and snoops from the other core. The pr

Datasheet 15Low Power Features2.1.2.2 Stop-Grant StateWhen the STPCLK# pin is asserted, each core of the quad-core processor enters the Stop-Grant sta

Low Power Features16 DatasheetIf RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin spe

Datasheet 17Low Power Features2.2 Enhanced Intel SpeedStep® TechnologyThe processor features Enhanced Intel SpeedStep Technology. Following are the ke

Low Power Features18 Datasheetoperating point. Upon receiving a break event from the package low power state, control will be returned to software whi

Datasheet 19Low Power Features2.4.1 Dual Intel Dynamic AccelerationThe processor supports Dual Intel Dynamic Acceleration. For any two cores in the qu

2 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO A

Low Power Features20 Datasheet

Datasheet 21Electrical Specifications3 Electrical Specifications3.1 Power and Ground PinsFor clean, on-chip power distribution, the processor will hav

Electrical Specifications22 Datasheet3.3 Voltage Identification and Power SequencingThe processor uses seven voltage identification pins,VID[6:0], to

Datasheet 23Electrical SpecificationsTable 3. Voltage Identification Definition (Sheet 1 of 4)VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)0 0 0 0 0 0 0

Electrical Specifications24 Datasheet01 001 0 11.037501 001 1 01.025001 001 1 11.012501 010 0 01.000001 010 0 10.987501 010 1 00.975001 010 1 10.96250

Datasheet 25Electrical Specifications1 0 0 1 0 1 1 0.56251 0 0 1 1 0 0 0.55001 0 0 1 1 0 1 0.53751 0 0 1 1 1 0 0.52501 0 0 1 1 1 1 0.51251 0 1 0 0 0 0

Electrical Specifications26 Datasheet3.4 Catastrophic Thermal ProtectionThe processor supports the THERMTRIP# signal for catastrophic thermal protecti

Datasheet 27Electrical Specifications3.6 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the proces

Electrical Specifications28 DatasheetNOTES:1. Refer to Chapter 4 for signal descriptions and termination requirements.2. In processor systems where th

Datasheet 29Electrical Specifications3.8 CMOS SignalsCMOS input signals are shown in Table 5. Legacy output FERR#, IERR# and other non-AGTL+ signals (

Datasheet 3Contents1Introduction...71.1 Ter

Electrical Specifications30 Datasheet3.10 Processor DC SpecificationsThe processor DC specifications in this section are defined at the processor core

Datasheet 31Electrical SpecificationsNOTES:1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at ma

Electrical Specifications32 DatasheetNOTES:1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at ma

Datasheet 33Electrical SpecificationsFigure 4. Active VCC and ICC Loadline for Quad-Core Extreme Mobile ProcessorICC-CORE max {HFM|LFM}VCC-CORE [V]VCC

Electrical Specifications34 DatasheetNOTE: Deeper Sleep mode tolerance depends on VID value.Figure 5. Deeper Sleep VCC and ICC Loadline for Quad-Core

Datasheet 35Electrical SpecificationsNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. VIL is de

Electrical Specifications36 DatasheetNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. The VCCP

Datasheet 37Package Mechanical Specifications and Pin Information4 Package Mechanical Specifications and Pin Information4.1 Package Mechanical Specifi

Package Mechanical Specifications and Pin Information38 DatasheetFigure 6. Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 1 of 2)0.65 MAX0.65

Datasheet 39Package Mechanical Specifications and Pin InformationFigure 7. Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 2 of 2) 13.976.98513

4 Datasheet Figures1 Core Low Power States...122 Package Lo

Package Mechanical Specifications and Pin Information40 Datasheet4.2 Processor Pinout and Pin ListFigure 8 and Figure 9 shows the processor pinout as

Datasheet 41Package Mechanical Specifications and Pin InformationFigure 9. Quad-Core Processor Pinout (Top Package View, Right Side)14 15 16 17 18 19

Package Mechanical Specifications and Pin Information42 DatasheetTable 12. Pin Listing by Pin NamePin NamePin #Signal Buffer TypeDirectionA20M# A6 CMO

Package Mechanical Specifications and Pin InformationDatasheet 43COMP[0] R26 Power/OtherInput/OutputCOMP[1] U26 Power/OtherInput/OutputCOMP[2] AA1 Pow

Package Mechanical Specifications and Pin Information44 DatasheetD[51]# AB22 Source SynchInput/OutputD[52]# AB21 Source SynchInput/OutputD[53]# AC26 S

Package Mechanical Specifications and Pin InformationDatasheet 45REQ[3]# J3 Source SynchInput/OutputREQ[4]# L1 Source SynchInput/OutputRESET# C1 Commo

Package Mechanical Specifications and Pin Information46 DatasheetVCC AE13 Power/OtherVCC AE15 Power/OtherVCC AE17 Power/OtherVCC AE18 Power/OtherVCC A

Package Mechanical Specifications and Pin InformationDatasheet 47VSS A2 Power/OtherVSS A4 Power/OtherVSS A8 Power/OtherVSS A11 Power/OtherVSS A14 Powe

Package Mechanical Specifications and Pin Information48 DatasheetVSS D13 Power/OtherVSS D16 Power/OtherVSS D19 Power/OtherVSS D23 Power/OtherVSS D26 P

Package Mechanical Specifications and Pin InformationDatasheet 49Table 13. Pin Listing by Pin NumberPin #Pin NameSignal Buffer TypeDirectionA2 VSS Pow

Datasheet 5Revision History§Document NumberRevision NumberDescription Date320390-001Initial Release August 2008320390-002• Updated Table 8: Added Q900

Package Mechanical Specifications and Pin Information50 DatasheetAB21 D[52]# Source SynchInput/OutputAB22 D[51]# Source SynchInput/OutputAB23 VSS Powe

Package Mechanical Specifications and Pin InformationDatasheet 51AE9 VCC Power/OtherAE10 VCC Power/OtherAE11 VSS Power/OtherAE12 VCC Power/OtherAE13 V

Package Mechanical Specifications and Pin Information52 DatasheetC3 TEST7 TestC4 IGNNE# CMOS InputC5 VSS Power/OtherC6 LINT0 CMOS InputC7THERMTRIP#Ope

Package Mechanical Specifications and Pin InformationDatasheet 53E23 D[7]# Source SynchInput/OutputE24 VSS Power/OtherE25 D[6]# Source SynchInput/Outp

Package Mechanical Specifications and Pin Information54 DatasheetJ6 VCCP Power/OtherJ21 VCCP Power/OtherJ22 VSS Power/OtherJ23 D[11]# Source SynchInpu

Package Mechanical Specifications and Pin InformationDatasheet 55P4 A[14]# Source SynchInput/OutputP5 A[11]# Source SynchInput/OutputP6 VSS Power/Othe

Package Mechanical Specifications and Pin Information56 DatasheetW3 A[32]# Source SynchInput/OutputW4 VSS Power/OtherW5 A[28]# Source SynchInput/Outpu

Datasheet 57Package Mechanical Specifications and Pin InformationTable 14. Signal Description (Sheet 1 of 9)Name Type DescriptionA20M# InputIf A20M#

Package Mechanical Specifications and Pin Information58 DatasheetBPM_2[1]#BPM_2[0;3:2]#OutputInput/OutputBPM_2[3:0]# (Breakpoint Monitor) are breakpoi

Datasheet 59Package Mechanical Specifications and Pin InformationD[63:0]#Input/OutputD[63:0]# (Data) are the data signals. These signals provide a 64-

6 Datasheet

Package Mechanical Specifications and Pin Information60 DatasheetDINV[3:0]#Input/OutputDINV[3:0]# (Data Bus Inversion) are source synchronous and indi

Datasheet 61Package Mechanical Specifications and Pin InformationFERR#/PBE# OutputFERR# (Floating-point Error)/PBE# (Pending Break Event) is a multipl

Package Mechanical Specifications and Pin Information62 DatasheetIGNNE# InputIGNNE# (Ignore Numeric Error) is asserted to force the processor to ignor

Datasheet 63Package Mechanical Specifications and Pin InformationPROCHOT#Input/OutputAs an output, PROCHOT# (Processor Hot) will go active when the pr

Package Mechanical Specifications and Pin Information64 DatasheetRSVDReserved/No ConnectThese pins are RESERVED and must be left unconnected on the bo

Datasheet 65Package Mechanical Specifications and Pin InformationTEST1,TEST2,TEST3,TEST4,TEST5, TEST6 TEST7InputRefer to the appropriate platform desi

Package Mechanical Specifications and Pin Information66 DatasheetTable 15. New Pins for the Quad-Core Mobile ProcessorPin Name Pin# DescriptionBPM_2[0

Datasheet 67Thermal Specifications and Design Considerations5 Thermal Specifications and Design ConsiderationsThe processor requires a thermal solutio

Thermal Specifications and Design Considerations68 Datasheet5. Processor TDP requirements in Intel Dynamic Acceleration mode are lesser than TDP in HF

Datasheet 69Thermal Specifications and Design ConsiderationsNOTES:1. Intel does not support or recommend operation of the thermal diode under reverse

Datasheet 7Introduction1 Introduction The Intel® CoreTM2 Extreme quad-core processor and Intel® CoreTM2 quad processor on 45-nanometer process technol

Thermal Specifications and Design Considerations70 Datasheettemperature. The Intel Thermal Monitor uses two modes to activate the TCC: automatic mode

Datasheet 71Thermal Specifications and Design ConsiderationsBesides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also inc

Thermal Specifications and Design Considerations72 DatasheetChanges to the temperature can be detected via two programmable thresholds located in the

Introduction8 DatasheetStorage ConditionsRefers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Process

Datasheet 9Introduction1.2 ReferencesMaterial and concepts available in the following documents may be beneficial when reading this document.NOTES:Con