Intel BX8060515750 Scheda Tecnica

Document Number: 322165-001Intel® Core™ i7-800 and i5-700 Desktop Processor SeriesDatasheet – Volume 2September 2009

10 Datasheet, Volume 24.10.28MC_CHANNEL_0_EW_BGF_SETTINGSMC_CHANNEL_1_EW_BGF_SETTINGS...2574.10.29M

Processor Integrated I/O (IIO) Configuration Registers100 Datasheet, Volume 28RO 0SERR EnableFor PCI Express/DMI ports, this field enables notifying t

Datasheet, Volume 2 101Processor Integrated I/O (IIO) Configuration Registers3.4.2.4 PCISTS—PCI Status RegisterThe PCI Status register is a 16-bit sta

Processor Integrated I/O (IIO) Configuration Registers102 Datasheet, Volume 212 RO 0Received Target AbortThis bit is set when a device experiences a

Datasheet, Volume 2 103Processor Integrated I/O (IIO) Configuration Registers3.4.2.5 RID—Revision Identification RegisterThis register contains the re

Processor Integrated I/O (IIO) Configuration Registers104 Datasheet, Volume 23.4.2.8 HDR—Header Type RegisterThis register identifies the header layou

Datasheet, Volume 2 105Processor Integrated I/O (IIO) Configuration Registers3.4.2.12 INTLIN—Interrupt Line RegisterThe Interrupt Line register is use

Processor Integrated I/O (IIO) Configuration Registers106 Datasheet, Volume 23.4.3.2 NXTPTR—PCI Express® Next Capability List RegisterThe PCI Express

Datasheet, Volume 2 107Processor Integrated I/O (IIO) Configuration Registers3.4.3.4 DEVCAP—PCI Express® Device Capabilities RegisterThe PCI Express D

Processor Integrated I/O (IIO) Configuration Registers108 Datasheet, Volume 23.4.3.5 DEVCTRL—PCI Express® Device Control RegisterThe PCI Express Devic

Datasheet, Volume 2 109Processor Integrated I/O (IIO) Configuration Registers1 RO 0Non Fatal Error Reporting EnableThis bit applies only to the PCI Ex

Datasheet, Volume 2 11MC_RIR_WAY_CH1_26; MC_RIR_WAY_CH1_27MC_RIR_WAY_CH1_28; MC_RIR_WAY_CH1_29MC_RIR_WAY_CH1_30; MC_RIR_WAY_CH1_31...

Processor Integrated I/O (IIO) Configuration Registers110 Datasheet, Volume 23.4.3.6 DEVSTS—PCI Express® Device Status RegisterThe PCI Express Device

Datasheet, Volume 2 111Processor Integrated I/O (IIO) Configuration Registers3.4.4 Intel® VT-d, Address Mapping, System Management Registers (Device 8

Processor Integrated I/O (IIO) Configuration Registers112 Datasheet, Volume 23.4.4.2 IIOMISCSS—Integrated I/O MISC StatusThis register can be used to

Datasheet, Volume 2 113Processor Integrated I/O (IIO) Configuration Registers3.4.4.4 TOLM—Top of Low MemoryTop of low memory. Note that bottom of low

Processor Integrated I/O (IIO) Configuration Registers114 Datasheet, Volume 23.4.4.7 NCMEM.LIMIT—NCMEM LimitLimit address of Intel QuickPath Interconn

Datasheet, Volume 2 115Processor Integrated I/O (IIO) Configuration Registers26 RWL 0Hide_Dev16_Fun0 When set, hide Device #16/Function #0When set, al

Processor Integrated I/O (IIO) Configuration Registers116 Datasheet, Volume 23RWL 0Hide_Dev3 When set, hide Device 31. This bit has no impact on any c

Datasheet, Volume 2 117Processor Integrated I/O (IIO) Configuration Registers3.4.4.9 DEVHIDE2—Device Hide 2 RegisterThis register provides a method to

Processor Integrated I/O (IIO) Configuration Registers118 Datasheet, Volume 23.4.4.10 IIOBUSNO—IIO Internal Bus Number3.4.4.11 LMMIOL.BASE—Local MMIOL

Datasheet, Volume 2 119Processor Integrated I/O (IIO) Configuration Registers3.4.4.12 LMMIOL.LIMIT—Local MMIOL Limit3.4.4.13 LMMIOH.BASE—Local MMIOH B

12 Datasheet, Volume 25.5 System Management Mode (SMM) ...2875.5.1 SMM Space Definit

Processor Integrated I/O (IIO) Configuration Registers120 Datasheet, Volume 23.4.4.15 LMMIOH.BASEU—Local MMIOH Base Upper3.4.4.16 LMMIOH.LIMITU—Local

Datasheet, Volume 2 121Processor Integrated I/O (IIO) Configuration Registers3.4.4.18 LCFGBUS.LIMIT—Local Configuration Bus Number Limit Register3.4.4

Processor Integrated I/O (IIO) Configuration Registers122 Datasheet, Volume 23.4.4.21 GMMIOH.BASE—Global MMIOH Base3.4.4.22 GMMIOH.LIMIT—Global MMIOH

Datasheet, Volume 2 123Processor Integrated I/O (IIO) Configuration Registers3.4.4.23 GMMIOH.BASEU—Global MMIOH Base Upper3.4.4.24 GMMIOH.LIMITU—Globa

Processor Integrated I/O (IIO) Configuration Registers124 Datasheet, Volume 23.4.4.26 GCFGBUS.LIMIT—Global Configuration Bus Number Limit Register3.4.

Datasheet, Volume 2 125Processor Integrated I/O (IIO) Configuration Registers3.4.4.29 VTBAR—Base Address Register for Intel® VT-d Chipset RegistersReg

Processor Integrated I/O (IIO) Configuration Registers126 Datasheet, Volume 23.4.4.30 VTGENCTRL—Intel® VT-d General Control RegisterRegister: VTGENCTR

Datasheet, Volume 2 127Processor Integrated I/O (IIO) Configuration Registers3.4.4.31 VTISOCHCTRL—Intel VT-d Isoch Related Control Register3.4.4.32 VT

Processor Integrated I/O (IIO) Configuration Registers128 Datasheet, Volume 23.4.4.33 VTSTS—Intel® VT-d Status Register3.4.5 Semaphore and ScratchPad

Datasheet, Volume 2 129Processor Integrated I/O (IIO) Configuration Registers3.4.5.4 SR[12:15]—Scratch Pad Register 12-15 (Non-Sticky)3.4.5.5 SR[16:17

Datasheet, Volume 2 13Figures2-1 Memory Map to PCI Express* Device Configuration Space...222-2 Processor Configura

Processor Integrated I/O (IIO) Configuration Registers130 Datasheet, Volume 23.4.5.8 CWR[4:7]—Conditional Write Registers 4-73.4.5.9 CWR[8:11]—Conditi

Datasheet, Volume 2 131Processor Integrated I/O (IIO) Configuration Registers3.4.5.11 CWR[16:17]—Conditional Write Registers 16-173.4.5.12 CWR[18:23]—

Processor Integrated I/O (IIO) Configuration Registers132 Datasheet, Volume 23.4.5.14 IR[4:7]—Increment Registers 4-73.4.5.15 IR[8:11]—Increment Regis

Datasheet, Volume 2 133Processor Integrated I/O (IIO) Configuration Registers3.4.5.17 IR[16:17]—Increment Registers 16-173.4.5.18 IR[18:23]—Increment

Processor Integrated I/O (IIO) Configuration Registers134 Datasheet, Volume 23.4.6 System Control/Status Registers (Device 8, Function 2)3.4.6.1 SYSMA

Datasheet, Volume 2 135Processor Integrated I/O (IIO) Configuration Registers3.4.6.3 SYRE—System ResetThis register controls IIO (Integrated I/O) Rese

Processor Integrated I/O (IIO) Configuration Registers136 Datasheet, Volume 23.4.7.2 IIOSLPSTS_H—IIO Sleep Status High Register3.4.7.3 PMUSTATE—Power

Datasheet, Volume 2 137Processor Integrated I/O (IIO) Configuration Registers3.4.7.4 CTSTS—Throttling Status Register3.4.7.5 CTCTRL—Throttling Control

Processor Integrated I/O (IIO) Configuration Registers138 Datasheet, Volume 23.5.1 Intel® VT-d Configuration Register Space (MMIO)Table 3-13. Intel® V

Datasheet, Volume 2 139Processor Integrated I/O (IIO) Configuration RegistersTable 3-14. Intel® VT-d Memory Mapped Registers — 100h–1FFh, 1100h–11FFhF

14 Datasheet, Volume 24-13 Device 4, Function 3 — Integrated Memory Controller Channel 0 Thermal Control Registers...

Processor Integrated I/O (IIO) Configuration Registers140 Datasheet, Volume 2 INVADDRREG200h280h204h284hIOTLBINV208h288h20Ch28Ch210h 290h214h 294h218h

Datasheet, Volume 2 141Processor Integrated I/O (IIO) Configuration Registers3.5.2 Register DescriptionIn the following sections, Intel VT-d registers

Processor Integrated I/O (IIO) Configuration Registers142 Datasheet, Volume 23.5.2.2 VTD_CAP[0:1]—Intel® VT-d Chipset Capabilities Register (Sheet 1 o

Datasheet, Volume 2 143Processor Integrated I/O (IIO) Configuration Registers3.5.2.3 EXT_VTD_CAP[0:1]—Extended Intel® VT-d Capability RegisterRegister

Processor Integrated I/O (IIO) Configuration Registers144 Datasheet, Volume 23.5.2.4 GLBCMD[0:1]—Global Command RegisterRegister: GLBCMD[0:1]Addr: MMI

Datasheet, Volume 2 145Processor Integrated I/O (IIO) Configuration Registers3.5.2.5 GLBSTS[0:1]—Global Status Register3.5.2.6 ROOTENTRYADD[0:1]—Root

Processor Integrated I/O (IIO) Configuration Registers146 Datasheet, Volume 23.5.2.7 CTXCMD[0:1]—Context Command RegisterRegister: CTXCMD[0:1]Addr: MM

Datasheet, Volume 2 147Processor Integrated I/O (IIO) Configuration Registers3.5.2.8 FLTSTS[0:1]—Fault Status RegisterRegister: FLTSTS[0:1]Addr: MMIOB

Processor Integrated I/O (IIO) Configuration Registers148 Datasheet, Volume 23.5.2.9 FLTEVTCTRL[0:1]—Fault Event Control RegisterRegister: FLTEVTCTRL[

Datasheet, Volume 2 149Processor Integrated I/O (IIO) Configuration Registers3.5.2.10 FLTEVTDATA[0:1]—Fault Event Data Register3.5.2.11 FLTEVTADDR[0:1

Datasheet, Volume 2 15Revision History§Revision NumberDescriptionRevision Date-001 Initial releaseSeptember 2009

Processor Integrated I/O (IIO) Configuration Registers150 Datasheet, Volume 23.5.2.14 PROT_LOW_MEM_BASE[0:1]—Protected Memory Low Base Register3.5.2.1

Datasheet, Volume 2 151Processor Integrated I/O (IIO) Configuration Registers3.5.2.17 PROT_HIGH_MEM_LIMIT[0:1]—Protected Memory Limit Base Register3.5

Processor Integrated I/O (IIO) Configuration Registers152 Datasheet, Volume 23.5.2.20 INV_QUEUE_ADD[0:1]—Invalidation Queue Address Register3.5.2.21 I

Datasheet, Volume 2 153Processor Integrated I/O (IIO) Configuration Registers3.5.2.22 INV_COMP_EVT_CTL[0:1]—Invalidation Completion Event Control Regi

Processor Integrated I/O (IIO) Configuration Registers154 Datasheet, Volume 23.5.2.25 INV_COMP_EVT_UPRADDR[0:1]—Invalidation Completion Event Upper Ad

Datasheet, Volume 2 155Processor Integrated I/O (IIO) Configuration Registers3.5.2.27 FLTREC[10,7:0]—Fault Record RegisterFLTREC[10] register is for t

Processor Integrated I/O (IIO) Configuration Registers156 Datasheet, Volume 23.5.2.29 IOTLBINV[0:1]—IOTLB Invalidate RegisterRegister: IOTLBINV[0:1]Ad

Datasheet, Volume 2 157Processor Integrated I/O (IIO) Configuration Registers3.6 Intel® Trusted Execution Technology (Intel® TXT) Register MapTable 3-

Processor Integrated I/O (IIO) Configuration Registers158 Datasheet, Volume 2Table 3-16. Intel® Trusted Execution Technology Registers, cont’dTXT.VER.

Datasheet, Volume 2 159Processor Integrated I/O (IIO) Configuration RegistersTable 3-17. Intel® Trusted Execution Technology Registers, cont’d200h 280

16 Datasheet, Volume 2

Processor Integrated I/O (IIO) Configuration Registers160 Datasheet, Volume 2Table 3-18. Intel® Trusted Execution Technology Registers, cont’dTXT.Heap

Datasheet, Volume 2 161Processor Integrated I/O (IIO) Configuration RegistersTable 3-19. Intel® Trusted Execution Technology Registers, cont’dTXT.Publ

Processor Integrated I/O (IIO) Configuration Registers162 Datasheet, Volume 23.6.1 Intel® TXT Space RegistersThe Intel TXT registers adhere to the pub

Datasheet, Volume 2 163Processor Integrated I/O (IIO) Configuration Registers14 RO 0TXT.LOCALITY3.OPEN.STSThis bit is set when the TXT.CMD.OPEN.LOCALI

Processor Integrated I/O (IIO) Configuration Registers164 Datasheet, Volume 23.6.1.2 TXT.ESTS—Intel® TXT Error Status RegisterThis register is used to

Datasheet, Volume 2 165Processor Integrated I/O (IIO) Configuration Registers3.6.1.3 TXT.THREADS.EXISTS—Intel® TXT Thread Exists RegisterThis register

Processor Integrated I/O (IIO) Configuration Registers166 Datasheet, Volume 23.6.1.5 TXT.ERRORCODE—Intel® TXT Error Code Register When software discov

Datasheet, Volume 2 167Processor Integrated I/O (IIO) Configuration Registers3.6.1.7 TXT.CMD.CLOSE_PRIVATE—Intel® TXT Close Private CommandRegisterThe

Processor Integrated I/O (IIO) Configuration Registers168 Datasheet, Volume 23.6.1.9 TXT.ID—Intel® TXT Identifier RegisterThis register holds TXT ID f

Datasheet, Volume 2 169Processor Integrated I/O (IIO) Configuration Registers3.6.1.11 TXT.CMD.UNLOCK.BASE—Intel® TXT Unlock Base Command RegisterWhen

Datasheet, Volume 2 17Introduction1 IntroductionThis is Volume 2 of the Datasheet for the Intel® Core™ i7-800 and i5-700 desktop processor series. The

Processor Integrated I/O (IIO) Configuration Registers170 Datasheet, Volume 23.6.1.13 TXT.SINIT.MEMORY.SIZE—Intel® TXT SINIT Memory Size RegisterThis

Datasheet, Volume 2 171Processor Integrated I/O (IIO) Configuration Registers3.6.1.15 TXT.HEAP.BASE—Intel® TXT HEAP Code Base RegisterThis register ho

Processor Integrated I/O (IIO) Configuration Registers172 Datasheet, Volume 23.6.1.17 TXT.MSEG.BASE—Intel® TXT MSEG Base RegisterThis register holds a

Datasheet, Volume 2 173Processor Integrated I/O (IIO) Configuration Registers3.6.1.19 TXT.SCRATCHPAD0—Intel® TXT Scratch Pad Register 0Intel TXT Scrat

Processor Integrated I/O (IIO) Configuration Registers174 Datasheet, Volume 23.6.1.21 TXT.CMD.OPEN.LOCALITY1—Intel® TXT Open Locality 1 CommandEnables

Datasheet, Volume 2 175Processor Integrated I/O (IIO) Configuration RegistersNote: PRIVATE space must also be Open for Locality 2 to be decoded as Int

Processor Integrated I/O (IIO) Configuration Registers176 Datasheet, Volume 23.7 Intel® QuickPath Interconnect Device/FunctionsThe following device/fu

Datasheet, Volume 2 177Processor Integrated I/O (IIO) Configuration Registers3.7.1 Intel® QuickPath Interconnect Link Layer RegistersThe link layer re

Processor Integrated I/O (IIO) Configuration Registers178 Datasheet, Volume 23.7.1.4 QPI[0]LCL—Intel® QuickPath Interconnect Link ControlRegister per

Datasheet, Volume 2 179Processor Integrated I/O (IIO) Configuration Registers3.7.1.5 QPI[0]LCRDC—Intel® QuickPath Interconnect Link Credit ControlRegi

Introduction18 Datasheet, Volume 2§RWORead/Write Once. A register bit with this attribute can be written to only once after power up. After the first

Processor Integrated I/O (IIO) Configuration Registers180 Datasheet, Volume 23.7.2 Intel® QuickPath Interconnect Routing & Protocol Layer Register

Datasheet, Volume 2 181Processor Integrated I/O (IIO) Configuration Registers3.7.2.1 QPIPCTRL0—Intel® QuickPath Interconnect Protocol Control 0Registe

Processor Integrated I/O (IIO) Configuration Registers182 Datasheet, Volume 23.7.2.3 CAPHDRH—PCI Express® Capability Header High RegisterCapability he

Datasheet, Volume 2 183Processor Uncore Configuration Registers4 Processor Uncore Configuration RegistersThe processor supports PCI configuration spac

Processor Uncore Configuration Registers184 Datasheet, Volume 24.2 Device MappingEach component in the processor is uniquely identified by a PCI bus a

Datasheet, Volume 2 185Processor Uncore Configuration Registers4.3 Detailed Configuration Space MapsTable 4-2. Device 0, Function 0 — Generic Non-core

Processor Uncore Configuration Registers186 Datasheet, Volume 2Table 4-3. Device 0, Function 1 — System Address Decoder RegistersDID VID 00h SAD_DRAM_

Datasheet, Volume 2 187Processor Uncore Configuration RegistersTable 4-4. Device 2, Function 0 — Intel® QuickPath Interconnect Link 0 RegistersDID VID

Processor Uncore Configuration Registers188 Datasheet, Volume 2Table 4-5. Device 2, Function 1 — Intel® QuickPath Interconnect Physical 0 RegistersDID

Datasheet, Volume 2 189Processor Uncore Configuration Registers Table 4-6. Device 3, Function 0 — Integrated Memory Controller RegistersDID VID 00h 80

Datasheet, Volume 2 19Configuration Process and Registers2 Configuration Process and Registers2.1 Platform Configuration StructureThe DMI physically c

Processor Uncore Configuration Registers190 Datasheet, Volume 2Table 4-7. Device 3, Function 1 — Target Address Decoder RegistersDID VID 00h TAD_DRAM_

Datasheet, Volume 2 191Processor Uncore Configuration RegistersTable 4-8. Device 3, Function 2 — Memory Controller Test RegistersDID VID 00h 80hPCISTS

Processor Uncore Configuration Registers192 Datasheet, Volume 2Table 4-9. Device 3, Function 4 — Integrated Memory Controller Test Registers DID VID 0

Datasheet, Volume 2 193Processor Uncore Configuration RegistersTable 4-10. Device 4, Function 0 — Integrated Memory Controller Channel 0 Control Regis

Processor Uncore Configuration Registers194 Datasheet, Volume 2Table 4-11. Device 4, Function 1 — Integrated Memory Controller Channel 0 Address Regis

Datasheet, Volume 2 195Processor Uncore Configuration RegistersTable 4-12. Device 4, Function 2 — Integrated Memory Controller Channel 0 Rank Register

Processor Uncore Configuration Registers196 Datasheet, Volume 2Table 4-13. Device 4, Function 3 — Integrated Memory Controller Channel 0 Thermal Contr

Datasheet, Volume 2 197Processor Uncore Configuration RegistersTable 4-14. Device 5, Function 0 — Integrated Memory Controller Channel 1 Control Regis

Processor Uncore Configuration Registers198 Datasheet, Volume 2Table 4-15. Device 5, Function 1 — Integrated Memory Controller Channel 1 Address Regis

Datasheet, Volume 2 199Processor Uncore Configuration RegistersTable 4-16. Device 5, Function 2 — Integrated Memory Controller Channel 1 Rank Register

2 Datasheet, Volume 2Legal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IM

Configuration Process and Registers20 Datasheet, Volume 2Control/Status registers and Function 4 contains miscellaneous control/status registers on po

Processor Uncore Configuration Registers200 Datasheet, Volume 2Table 4-17. Device 5, Function 3 — Integrated Memory Controller Channel 1 Thermal Contr

Datasheet, Volume 2 201Processor Uncore Configuration Registers4.4 PCI Standard RegistersThese registers appear in every function for every device.4.4

Processor Uncore Configuration Registers202 Datasheet, Volume 24.4.3 RID—Revision Identification RegisterThis register contains the revision number of

Datasheet, Volume 2 203Processor Uncore Configuration Registers4.4.3.1 Stepping Revision ID (SRID)This register contains the revision number of the pr

Processor Uncore Configuration Registers204 Datasheet, Volume 24.4.4 CCR—Class Code RegisterThis register contains the Class Code for the device. Writ

Datasheet, Volume 2 205Processor Uncore Configuration Registers4.4.5 HDR—Header Type RegisterThis register identifies the header layout of the configu

Processor Uncore Configuration Registers206 Datasheet, Volume 24.4.7 SID—Subsystem IdentityThis register identifies the system. It appears in every fu

Datasheet, Volume 2 207Processor Uncore Configuration Registers4.4.8 PCICMD—Command RegisterThis register defines the PCI 3.0 compatible command regis

Processor Uncore Configuration Registers208 Datasheet, Volume 24.4.9 PCISTS—PCI Status RegisterThe PCI Status register is a 16-bit status register tha

Datasheet, Volume 2 209Processor Uncore Configuration Registers4.5 SAD—System Address Decoder Registers4.5.1 SAD_PAM0123Register for legacy device 0,

Datasheet, Volume 2 21Configuration Process and Registers2.2 Configuration MechanismsThe processor is the originator of configuration cycles. Internal

Processor Uncore Configuration Registers210 Datasheet, Volume 227:26 RO 0 Reserved25:24 RW 0PAM3_LOENABLE. 0D0000h–0D3FFFh Attribute (LOENABLE) This f

Datasheet, Volume 2 211Processor Uncore Configuration Registers4.5.2 SAD_PAM456Register for legacy device 0, function 0, 94h-97h address space.Device:

Processor Uncore Configuration Registers212 Datasheet, Volume 24.5.3 SAD_HENRegister for legacy Hole Enable.4.5.4 SAD_SMRAMRegister for legacy 9Dh add

Datasheet, Volume 2 213Processor Uncore Configuration Registers4.5.5 SAD_PCIEXBARGlobal register for PCI ExpressXBAR address space.4.5.6 SAD_TPCIEXBAR

Processor Uncore Configuration Registers214 Datasheet, Volume 24.5.7 SAD_MCSEG_BASEGlobal register for McSEG address space. These are designed to look

Datasheet, Volume 2 215Processor Uncore Configuration Registers4.5.9 SAD_MESEG_BASERegister for Intel Management Engine (Intel ME) range base address.

Processor Uncore Configuration Registers216 Datasheet, Volume 24.5.11 SAD_DRAM_RULE_0; SAD_DRAM_RULE_1SAD_DRAM_RULE_2; SAD_DRAM_RULE_3SAD_DRAM_RULE_4;

Datasheet, Volume 2 217Processor Uncore Configuration Registers4.5.12 SAD_INTERLEAVE_LIST_0; SAD_INTERLEAVE_LIST_1SAD_INTERLEAVE_LIST_2; SAD_INTERLEAV

Processor Uncore Configuration Registers218 Datasheet, Volume 24.6 Intel® QuickPath Interconnect Link Registers4.6.1 QPI_QPILCL_L0Intel QuickPath Inte

Datasheet, Volume 2 219Processor Uncore Configuration Registers5:4 RWST 0LLR_TO_LINK_RESET Consecutive LLRs to Link Reset — Sticky, Late action.00 = u

Configuration Process and Registers22 Datasheet, Volume 2the base address for the block of addresses below 4 GB for the configuration space associated

Processor Uncore Configuration Registers220 Datasheet, Volume 24.7 Integrated Memory Controller Control Registers4.7.1 MC_CONTROLPrimary control regis

Datasheet, Volume 2 221Processor Uncore Configuration Registers4.7.2 MC_SMI_DIMM_ERROR_STATUSSMI DIMM error threshold overflow status register. This b

Processor Uncore Configuration Registers222 Datasheet, Volume 24.7.4 MC_STATUSMC Primary Status register.4.7.5 MC_RESET_CONTROLDIMM Reset enabling con

Datasheet, Volume 2 223Processor Uncore Configuration Registers4.7.6 MC_CHANNEL_MAPPERChannel mapping register. The sequence of operations to update t

Processor Uncore Configuration Registers224 Datasheet, Volume 24.7.8 MC_CFG_LOCKBIOS must write the MC_CFG_LOCK bit after configuration is complete to

Datasheet, Volume 2 225Processor Uncore Configuration Registers4.7.9 MC_RD_CRDT_INITThese registers contain the initial read credits available for iss

Processor Uncore Configuration Registers226 Datasheet, Volume 24.7.10 MC_CRDT_WR_THLDMemory Controller Write Credit Thresholds. A Write threshold is d

Datasheet, Volume 2 227Processor Uncore Configuration Registers4.8 TAD—Target Address Decoder Registers4.8.1 TAD_DRAM_RULE_0; TAD_DRAM_RULE_1TAD_DRAM_

Processor Uncore Configuration Registers228 Datasheet, Volume 24.8.2 TAD_INTERLEAVE_LIST_0; TAD_INTERLEAVE_LIST_1TAD_INTERLEAVE_LIST_2; TAD_INTERLEAVE

Datasheet, Volume 2 229Processor Uncore Configuration Registers4.9 Integrated Memory Controller Test Registers4.9.1 Integrated Memory Controller Padsc

Datasheet, Volume 2 23Configuration Process and Registers2.3 Routing Configuration AccessesThe processor supports two PCI related interfaces: DMI and

Processor Uncore Configuration Registers230 Datasheet, Volume 2The mask and halt bits are defined as shown in Table 4-20.There are 3 registers defined

Datasheet, Volume 2 231Processor Uncore Configuration RegistersA write operation is performed by writing the payload in the data register including ma

Processor Uncore Configuration Registers232 Datasheet, Volume 24.9.3 MC_DIMM_CLK_RATIORequested DIMM clock ratio (Qclk). This is the data rate going t

Datasheet, Volume 2 233Processor Uncore Configuration Registers4.9.5 MC_TEST_PH_CTRMemory test Control Register4.9.6 MC_TEST_PH_PISMemory test physica

Processor Uncore Configuration Registers234 Datasheet, Volume 24.9.7 MC_TEST_PAT_GCTRPattern Generator Control.Device: 3Function: 4Offset: A8hAccess a

Datasheet, Volume 2 235Processor Uncore Configuration Registers4.9.8 MC_TEST_PAT_BAMemory Test Pattern Generator Buffer.4.9.9 MC_TEST_PAT_ISMemory tes

Processor Uncore Configuration Registers236 Datasheet, Volume 24.9.11 MC_TEST_EP_SCCTLMemory test electrical parameter scan chain control register.4.9

Datasheet, Volume 2 237Processor Uncore Configuration Registers4.10 Integrated Memory Controller Channel Control Registers4.10.1 MC_CHANNEL_0_DIMM_RES

Processor Uncore Configuration Registers238 Datasheet, Volume 24.10.2 MC_CHANNEL_0_DIMM_INIT_CMDMC_CHANNEL_1_DIMM_INIT_CMDIntegrated Memory Controller

Datasheet, Volume 2 239Processor Uncore Configuration Registers4.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMSMC_CHANNEL_1_DIMM_INIT_PARAMSInitialization sequenc

Configuration Process and Registers24 Datasheet, Volume 22.3.1 Internal Device Configuration AccessesThe processor decodes the Bus Number (Bits 23:16)

Processor Uncore Configuration Registers240 Datasheet, Volume 24.10.4 MC_CHANNEL_0_DIMM_INIT_STATUSMC_CHANNEL_1_DIMM_INIT_STATUSThe initialization sta

Datasheet, Volume 2 241Processor Uncore Configuration Registers4.10.5 MC_CHANNEL_0_DDR3CMDMC_CHANNEL_1_DDR3CMDDDR3 Configuration Command. This registe

Processor Uncore Configuration Registers242 Datasheet, Volume 24.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORTMC_CHANNEL_1_REFRESH_THROTTLE_SUPPORTThis r

Datasheet, Volume 2 243Processor Uncore Configuration Registers4.10.8 MC_CHANNEL_0_MRS_VALUE_2MC_CHANNEL_1_MRS_VALUE_2The initial MRS register values

Processor Uncore Configuration Registers244 Datasheet, Volume 24.10.9 MC_CHANNEL_0_RANK_PRESENTMC_CHANNEL_1_RANK_PRESENTThis register provides the ran

Datasheet, Volume 2 245Processor Uncore Configuration Registers4.10.10 MC_CHANNEL_0_RANK_TIMING_AMC_CHANNEL_1_RANK_TIMING_AThis register contains para

Processor Uncore Configuration Registers246 Datasheet, Volume 214:11 RW 0tdrRdTWr Minimum delay between Read followed by a write to different ranks on

Datasheet, Volume 2 247Processor Uncore Configuration Registers4.10.11 MC_CHANNEL_0_RANK_TIMING_BMC_CHANNEL_1_RANK_TIMING_BThis register contains para

Processor Uncore Configuration Registers248 Datasheet, Volume 24.10.12 MC_CHANNEL_0_BANK_TIMINGMC_CHANNEL_1_BANK_TIMINGThis register contains paramete

Datasheet, Volume 2 249Processor Uncore Configuration Registers4.10.14 MC_CHANNEL_0_CKE_TIMINGMC_CHANNEL_1_CKE_TIMINGThis register contains parameters

Datasheet, Volume 2 25Configuration Process and Registers2.3.2.2 DMI Configuration AccessesAccesses to disabled processor internal devices, bus number

Processor Uncore Configuration Registers250 Datasheet, Volume 24.10.15 MC_CHANNEL_0_ZQ_TIMINGMC_CHANNEL_1_ZQ_TIMINGThis register contains parameters t

Datasheet, Volume 2 251Processor Uncore Configuration Registers4.10.17 MC_CHANNEL_0_ODT_PARAMS1MC_CHANNEL_1_ODT_PARAMS1This register contains paramete

Processor Uncore Configuration Registers252 Datasheet, Volume 24.10.18 MC_CHANNEL_0_ODT_PARAMS2MC_CHANNEL_1_ODT_PARAMS2This register contains paramete

Datasheet, Volume 2 253Processor Uncore Configuration Registers4.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RDMC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RDThis regi

Processor Uncore Configuration Registers254 Datasheet, Volume 24.10.23 MC_CHANNEL_0_WAQ_PARAMSMC_CHANNEL_1_WAQ_PARAMSThis register contains parameters

Datasheet, Volume 2 255Processor Uncore Configuration Registers4.10.24 MC_CHANNEL_0_SCHEDULER_PARAMSMC_CHANNEL_1_SCHEDULER_PARAMSThese are the paramet

Processor Uncore Configuration Registers256 Datasheet, Volume 24.10.26 MC_CHANNEL_0_TX_BG_SETTINGSMC_CHANNEL_1_TX_BG_SETTINGSThese are the parameters

Datasheet, Volume 2 257Processor Uncore Configuration Registers4.10.27 MC_CHANNEL_0_RX_BGF_SETTINGSMC_CHANNEL_1_RX_BGF_SETTINGSThese are the parameter

Processor Uncore Configuration Registers258 Datasheet, Volume 24.10.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGSMC_CHANNEL_1_EW_BGF_OFFSET_SETTINGSThese are

Datasheet, Volume 2 259Processor Uncore Configuration Registers4.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1MC_CHANNEL_1_PAGETABLE_PARAMS1These are the param

Configuration Process and Registers26 Datasheet, Volume 2In addition to reserved bits within a register, the processor contains address locations in t

Processor Uncore Configuration Registers260 Datasheet, Volume 24.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1Channel

Datasheet, Volume 2 261Processor Uncore Configuration Registers4.11 Integrated Memory Controller Channel Address Registers4.11.1 MC_DOD_CH0_0MC_DOD_CH

Processor Uncore Configuration Registers262 Datasheet, Volume 24.11.2 MC_DOD_CH1_0MC_DOD_CH1_1Channel 1 DIMM Organization Descriptor Register.Device:

Datasheet, Volume 2 263Processor Uncore Configuration Registers4.11.3 MC_SAG_CH0_0; MC_SAG_CH0_1; MC_SAG_CH0_2; MC_SAG_CH0_3; MC_SAG_CH0_4; MC_SAG_CH0

Processor Uncore Configuration Registers264 Datasheet, Volume 24.11.4 MC_SAG_CH1_0; MC_SAG_CH1_1; MC_SAG_CH1_2; MC_SAG_CH1_3; MC_SAG_CH1_4; MC_SAG_CH1

Datasheet, Volume 2 265Processor Uncore Configuration Registers4.12 Integrated Memory Controller Channel Rank Registers4.12.1 MC_RIR_LIMIT_CH0_0; MC_R

Processor Uncore Configuration Registers266 Datasheet, Volume 24.12.3 MC_RIR_WAY_CH0_0; MC_RIR_WAY_CH0_1; MC_RIR_WAY_CH0_2; MC_RIR_WAY_CH0_3; MC_RIR_W

Datasheet, Volume 2 267Processor Uncore Configuration Registers4.12.4 MC_RIR_WAY_CH1_0; MC_RIR_WAY_CH1_1MC_RIR_WAY_CH1_2; MC_RIR_WAY_CH1_3MC_RIR_WAY_C

Processor Uncore Configuration Registers268 Datasheet, Volume 24.13 Memory Thermal Control4.13.1 MC_THERMAL_CONTROL0MC_THERMAL_CONTROL1Controls for th

Datasheet, Volume 2 269Processor Uncore Configuration Registers4.13.3 MC_THERMAL_DEFEATURE0MC_THERMAL_DEFEATURE1Thermal Throttle defeature register.4.

Datasheet, Volume 2 27Processor Integrated I/O (IIO) Configuration Registers3 Processor Integrated I/O (IIO) Configuration Registers3.1 Processor IIO

Processor Uncore Configuration Registers270 Datasheet, Volume 24.13.5 MC_THERMAL_PARAMS_B0MC_THERMAL_PARAMS_B1Parameters used by the thermal throttlin

Datasheet, Volume 2 271Processor Uncore Configuration Registers4.13.7 MC_CLOSED_LOOP0MC_CLOSED_LOOP1This register controls the closed loop thermal res

Processor Uncore Configuration Registers272 Datasheet, Volume 24.13.9 MC_RANK_VIRTUAL_TEMP0MC_RANK_VIRTUAL_TEMP1This register contains the 8 most sign

Datasheet, Volume 2 273Processor Uncore Configuration Registers4.13.11 MC_DDR_THERM_STATUS0MC_DDR_THERM_STATUS1This register contains the status porti

Processor Uncore Configuration Registers274 Datasheet, Volume 2

Datasheet, Volume 2 275System Address Map5 System Address Map5.1 IntroductionThis chapter provides a basic overview of the system address map and desc

System Address Map276 Datasheet, Volume 2The processor supports PCI Express* upper pre-fetchable base/limit registers. This allows the PCI Express uni

Datasheet, Volume 2 277System Address Map5.2.1 System Address MapFigure 5-1. System address Map16MB1MB1MB1MB64 MB –256 MB1MB8MB0A_0000C_0000E_00001 MB

System Address Map278 Datasheet, Volume 25.2.2 System DRAM Memory RegionsThese address ranges are always mapped to system DRAM memory, regardless of t

Datasheet, Volume 2 279System Address Map5.2.3 VGA/SMM and Legacy C/D/E/F RegionsFigure 5-2 shows the memory address regions below 1 MB. These regions

Processor Integrated I/O (IIO) Configuration Registers28 Datasheet, Volume 23.2 Device MappingAll devices on the Integrated I/O Module reside on PCI B

System Address Map280 Datasheet, Volume 2The VGA memory address range can also be mapped to system memory in SMM. IIO is totally transparent to the wo

Datasheet, Volume 2 281System Address Map5.2.4.1 Relocatable TSEGThese are system DRAM memory regions that are used for SMM/CMM mode operation. IIO wo

System Address Map282 Datasheet, Volume 25.2.5.2 MMIOLThis region is used for PCIe device memory addressing below 4 GB. Each IIO in the system is allo

Datasheet, Volume 2 283System Address Map5.2.5.6 Local XAPICThe processor Interrupt space is the address used to deliver interrupts to the processor(s

System Address Map284 Datasheet, Volume 25.2.6 Address Regions above 4 GB5.2.6.1 High System MemoryThis region is used to describe the address range o

Datasheet, Volume 2 285System Address Map5.2.6.3 BIOS Notes on Address Allocation above 4 GBThe processor does not support hot added memory. Hence, no

System Address Map286 Datasheet, Volume 25.3.2 ISA AddressesIIO supports ISA addressing per the PCI-PCI Bridge 1.2 Specification. ISA addressing is en

Datasheet, Volume 2 287System Address Mapremote peer-to-peer. Refer to section Section 5.8.1 and Section 5.8.2 for details of how these registers are

System Address Map288 Datasheet, Volume 25.5.2 SMM Space RestrictionsIf any of the following conditions are violated the results of SMM accesses are u

Datasheet, Volume 2 289System Address Map5.5.4 SMM Control CombinationsThe G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit al

Datasheet, Volume 2 29Processor Integrated I/O (IIO) Configuration Registerstreated as static in the sense that they will not be changed without the d

System Address Map290 Datasheet, Volume 2PCI Express and DMI Interface read accesses to the GMADR range are not supported therefore will have no addre

Datasheet, Volume 2 291System Address Map5.8 IIO Address DecodingIn general, software needs to guarantee that for a given address there can only be a

System Address Map292 Datasheet, Volume 2bit. There is no decode enable bit for configuration cycle decoding towards either a PCIe port or the interna

Datasheet, Volume 2 293System Address Map5.8.1.4 Summary of Outbound Target Decoder EntriesTable 5-4 provides a list of all the target decoder entries

System Address Map294 Datasheet, Volume 2Table 5-6 details IIO behavior for configuration requests from Intel QuickPath Interconnect and peer-to-peer

Datasheet, Volume 2 295System Address Map5.8.2 Inbound Address DecodingThis section covers the decoding that is done on any transaction that is receiv

System Address Map296 Datasheet, Volume 25.8.2.2 Summary of Inbound Address DecodingTable 5-8 summarizes IIO behavior on inbound memory transactions f

Datasheet, Volume 2 297System Address MapNotes:1. Note that VTBAR range would be within the MMIOL range of that IIO. And by that token, VTBAR range ca

System Address Map298 Datasheet, Volume 2Table 5-9 summarizes IIO behavior on inbound I/O transactions from any PCIe port.Notes:1. Inbound I/O is enab

Datasheet, Volume 2 299System Address MapTable 5-10 summarizes IIO behavior on inbound configuration transactions from any PCIe port.Notes:1. When for

Datasheet, Volume 2 3Contents1Introduction...

Processor Integrated I/O (IIO) Configuration Registers30 Datasheet, Volume 2Figure 3-1 illustrates how each PCI Express port’s configuration space app

System Address Map300 Datasheet, Volume 25.8.3 Intel® VT-d Address Map ImplicationsIntel VT-d applies only to inbound memory transactions. Inbound I/O

Datasheet, Volume 2 31Processor Integrated I/O (IIO) Configuration RegistersTable 3-2. Device 0 (DMI) Configuration MapDID VID 00h 80hPCISTS PCICMD 04

Processor Integrated I/O (IIO) Configuration Registers32 Datasheet, Volume 2Table 3-3. Device 0 (DMI) Extended Configuration Map100hPERFCTRLSTS180h104

Datasheet, Volume 2 33Processor Integrated I/O (IIO) Configuration RegistersTable 3-4. Device 3,5 PCI Express* Registers Legacy Configuration MapDID V

Processor Integrated I/O (IIO) Configuration Registers34 Datasheet, Volume 2Table 3-5. Device 3,5 PCI Express* Registers Extended Configuration Map100

Datasheet, Volume 2 35Processor Integrated I/O (IIO) Configuration Registers3.3.3 Standard PCI Configuration Space (0h to 3Fh) — Type 0/1 Common Confi

Processor Integrated I/O (IIO) Configuration Registers36 Datasheet, Volume 23.3.3.3 PCICMD—PCI Command RegisterThis register defines the PCI 3.0 compa

Datasheet, Volume 2 37Processor Integrated I/O (IIO) Configuration Registers (Sheet 1 of 2)Register: PCICMDDevice: 3,5 (PCIe*)Function: 0Offset: 04hB

Processor Integrated I/O (IIO) Configuration Registers38 Datasheet, Volume 23.3.3.4 PCISTS—PCI Status RegisterThe PCI Status register is a 16-bit stat

Datasheet, Volume 2 39Processor Integrated I/O (IIO) Configuration Registers13 RW1C 0Received Master Abort StatusThis bit is set when a device experie

4 Datasheet, Volume 23.3.4.2 SNXTPTR—Subsystem ID Next Pointer ...513.3.4.3 SVID—Subsystem Vendor ID ...

Processor Integrated I/O (IIO) Configuration Registers40 Datasheet, Volume 23.3.3.5 RID—Revision Identification RegisterThis register contains the rev

Datasheet, Volume 2 41Processor Integrated I/O (IIO) Configuration Registers3.3.3.7 CLSR—Cacheline Size Register3.3.3.8 PLAT—Primary Latency TimerThe

Processor Integrated I/O (IIO) Configuration Registers42 Datasheet, Volume 23.3.3.10 SVID—Subsystem Vendor IDThis register identifies the vendor of th

Datasheet, Volume 2 43Processor Integrated I/O (IIO) Configuration Registers3.3.3.14 INTPIN—Interrupt Pin RegisterThe INTP register identifies legacy

Processor Integrated I/O (IIO) Configuration Registers44 Datasheet, Volume 23.3.3.17 SUBBUS—Subordinate Bus Number RegisterThis register identifies th

Datasheet, Volume 2 45Processor Integrated I/O (IIO) Configuration Registers3.3.3.19 IOLIM—I/O Limit RegisterThe I/O Base register defines an address

Processor Integrated I/O (IIO) Configuration Registers46 Datasheet, Volume 23.3.3.20 SECSTS—Secondary Status RegisterSecondary Status register is a 16

Datasheet, Volume 2 47Processor Integrated I/O (IIO) Configuration Registers3.3.3.21 MBAS—Memory BaseThe Memory Base and Memory Limit registers define

Processor Integrated I/O (IIO) Configuration Registers48 Datasheet, Volume 23.3.3.23 PMBASE—Prefetchable Memory Base RegisterThe Prefetchable Memory B

Datasheet, Volume 2 49Processor Integrated I/O (IIO) Configuration Registers3.3.3.25 PMBASEU—Prefetchable Memory Base (Upper 32 bits)The Prefetchable

Datasheet, Volume 2 53.4.2.4 PCISTS—PCI Status Register... 1013.4.2.5 RID—Revision Identification Reg

Processor Integrated I/O (IIO) Configuration Registers50 Datasheet, Volume 23.3.3.27 BCTRL—Bridge Control RegisterThe Bridge Control register provides

Datasheet, Volume 2 51Processor Integrated I/O (IIO) Configuration Registers3.3.4 Device-Specific PCI Configuration Space — 40h to FFh3.3.4.1 SCAPID—S

Processor Integrated I/O (IIO) Configuration Registers52 Datasheet, Volume 23.3.4.3 SVID—Subsystem Vendor ID3.3.4.4 SID—Subsystem Identity3.3.4.5 DMIR

Datasheet, Volume 2 53Processor Integrated I/O (IIO) Configuration Registers3.3.4.6 MSICAPID—MSI Capability ID3.3.4.7 MSINXTPTR—MSI Next Pointer3.3.4.

Processor Integrated I/O (IIO) Configuration Registers54 Datasheet, Volume 23.3.4.9 MSIAR—MSI Address RegisterThe MSI Address Register (MSIAR) contain

Datasheet, Volume 2 55Processor Integrated I/O (IIO) Configuration Registers3.3.4.10 MSIDR—MSI Data RegisterThe MSI Data Register contains all the dat

Processor Integrated I/O (IIO) Configuration Registers56 Datasheet, Volume 23.3.4.12 MSIPENDING—MSI Pending Bit RegisterThe Mask Pending register enab

Datasheet, Volume 2 57Processor Integrated I/O (IIO) Configuration Registers3.3.4.15 PEGCAP—PCI Express* Capabilities RegisterThe PCI Express Capabili

Processor Integrated I/O (IIO) Configuration Registers58 Datasheet, Volume 23.3.4.16 DEVCAP—PCI Express* Device Capabilities RegisterThe PCI Express D

Datasheet, Volume 2 59Processor Integrated I/O (IIO) Configuration Registers3.3.4.17 DEVCTRL—PCI Express* Device Control Register The PCI Express Devi

6 Datasheet, Volume 23.4.5.8 CWR[4:7]—Conditional Write Registers 4-7...1303.4.5.9 CWR[8:11]—Conditional Write Registers

Processor Integrated I/O (IIO) Configuration Registers60 Datasheet, Volume 21RW 0Non Fatal Error Reporting EnableApplies only to the PCI Express/DMI p

Datasheet, Volume 2 61Processor Integrated I/O (IIO) Configuration Registers3.3.4.18 DEVSTS—PCI Express* Device Status RegisterThe PCI Express Device

Processor Integrated I/O (IIO) Configuration Registers62 Datasheet, Volume 23.3.4.19 LNKCAP—PCI Express* Link Capabilities RegisterThe Link Capabiliti

Datasheet, Volume 2 63Processor Integrated I/O (IIO) Configuration Registers9:4 RWO 010000b Maximum Link WidthThis field indicates the maximum width

Processor Integrated I/O (IIO) Configuration Registers64 Datasheet, Volume 23.3.4.20 LNKCON—PCI Express* Link Control Register (Device 0)The PCI Expre

Datasheet, Volume 2 65Processor Integrated I/O (IIO) Configuration Registers3.3.4.21 LNKCON—PCI Express* Link Control RegisterThe PCI Express Link Con

Processor Integrated I/O (IIO) Configuration Registers66 Datasheet, Volume 23.3.4.22 LNKSTS—PCI Express* Link Status RegisterThe PCI Express Link Stat

Datasheet, Volume 2 67Processor Integrated I/O (IIO) Configuration Registers9:4 RO 0hNegotiated Link WidthThis field indicates the negotiated width of

Processor Integrated I/O (IIO) Configuration Registers68 Datasheet, Volume 23.3.4.23 SLTCAP—PCI Express* Slot Capabilities RegisterThe Slot Capabiliti

Datasheet, Volume 2 69Processor Integrated I/O (IIO) Configuration Registers3.3.4.24 SLTCON—PCI Express* Slot Control RegisterThe Slot Control registe

Datasheet, Volume 2 73.5.2.26 INTR_REMAP_TABLE_BASE[0:1]—Interrupt Remapping Table Base Address Register...

Processor Integrated I/O (IIO) Configuration Registers70 Datasheet, Volume 23.3.4.25 ROOTCON—PCI Express* Root Control RegisterThe PCI Express Root Co

Datasheet, Volume 2 71Processor Integrated I/O (IIO) Configuration Registers3.3.4.26 ROOTCAP—PCI Express* Root Capabilities RegisterThe PCI Express Ro

Processor Integrated I/O (IIO) Configuration Registers72 Datasheet, Volume 23.3.4.27 ROOTSTS—PCI Express* Root Status RegisterThe PCI Express Root Sta

Datasheet, Volume 2 73Processor Integrated I/O (IIO) Configuration Registers3.3.4.28 DEVCAP2—PCI Express* Device Capabilities Register 2Register: DEVC

Processor Integrated I/O (IIO) Configuration Registers74 Datasheet, Volume 23.3.4.29 DEVCTRL2—PCI Express* Device Control Register 2Register: DEVCTRL2

Datasheet, Volume 2 75Processor Integrated I/O (IIO) Configuration Registers3.3.4.30 LNKCON2—PCI Express* Link Control Register 2Register: LNKCON2Devi

Processor Integrated I/O (IIO) Configuration Registers76 Datasheet, Volume 23.3.4.31 LNKSTS2—PCI Express* Link Control Register 23.3.4.32 PMCAP—Power

Datasheet, Volume 2 77Processor Integrated I/O (IIO) Configuration Registers3.3.4.33 PMCSR—Power Management Control and Status Register (Device 0 DMI)

Processor Integrated I/O (IIO) Configuration Registers78 Datasheet, Volume 23.3.4.34 PMCSR—Power Management Control and Status RegisterThis register p

Datasheet, Volume 2 79Processor Integrated I/O (IIO) Configuration Registers3.3.5 PCIe/DMI Extended Configuration SpaceThis section describes the exte

8 Datasheet, Volume 24.4.3.2 Compatible Revision ID (CRID) ...2034.4.4 CCR—Class Code Register...

Processor Integrated I/O (IIO) Configuration Registers80 Datasheet, Volume 220:16 RW 18hNumber of Outstanding RFOs/Pre-Allocated Non-Posted Requests f

Datasheet, Volume 2 81Processor Integrated I/O (IIO) Configuration Registers3.3.5.4 MISCCTRLSTS—Miscellaneous Control and Status Register (Sheet 1 of

Processor Integrated I/O (IIO) Configuration Registers82 Datasheet, Volume 227 RWS 0System Interrupt Only on Link BW/Management StatusThis bit, when s

Datasheet, Volume 2 83Processor Integrated I/O (IIO) Configuration Registers3.3.5.5 CTOCTRL—Completion Time-out Control Register1RWO 0hInbound Configu

Processor Integrated I/O (IIO) Configuration Registers84 Datasheet, Volume 23.3.6 DMI Root Complex Register BlockThis block is mapped into memory spac

Datasheet, Volume 2 85Processor Integrated I/O (IIO) Configuration Registers3.3.6.1 DMIVCH—DMI Virtual Channel Capability HeaderThis register Indicate

Processor Integrated I/O (IIO) Configuration Registers86 Datasheet, Volume 23.3.6.3 DMIVCCAP2—DMI Port VC Capability Register 2This register Describes

Datasheet, Volume 2 87Processor Integrated I/O (IIO) Configuration Registers3.3.6.5 DMIVC0RCAP—DMI VC0 Resource Capability3.3.6.6 DMIVC0RCTL—DMI VC0 R

Processor Integrated I/O (IIO) Configuration Registers88 Datasheet, Volume 23.3.6.7 DMIVC0RSTS—DMI VC0 Resource StatusReports the Virtual Channel spec

Datasheet, Volume 2 89Processor Integrated I/O (IIO) Configuration Registers3.3.6.9 DMIVC1RCTL—DMI VC1 Resource ControlControls the resources associat

Datasheet, Volume 2 94.9.9 MC_TEST_PAT_IS... 2354.9.10 MC_TEST_PAT_DCD .

Processor Integrated I/O (IIO) Configuration Registers90 Datasheet, Volume 23.3.6.10 DMIVC1RSTS—DMI VC1 Resource StatusReports the Virtual Channel spe

Datasheet, Volume 2 91Processor Integrated I/O (IIO) Configuration Registers3.3.6.12 DMILCTRL—DMI Link ControlThis register allows control of DMI.3.3.

Processor Integrated I/O (IIO) Configuration Registers92 Datasheet, Volume 23.4 Integrated I/O Core Registers (Device 8, Function 0-3)This section des

Datasheet, Volume 2 93Processor Integrated I/O (IIO) Configuration RegistersTable 3-8. Core Registers (Device 8, Function 0) — Offset 100h–1FFhReserve

Processor Integrated I/O (IIO) Configuration Registers94 Datasheet, Volume 2Table 3-9. Core Registers (Device 8, Function 1) — Semaphore and ScratchPa

Datasheet, Volume 2 95Processor Integrated I/O (IIO) Configuration RegistersTable 3-10. Core Registers (Device 8, Function 1) — Semaphore and ScratchP

Processor Integrated I/O (IIO) Configuration Registers96 Datasheet, Volume 2Table 3-11. Core Registers (Device 8, Function 2) — System Control/Status

Datasheet, Volume 2 97Processor Integrated I/O (IIO) Configuration RegistersTable 3-12. Core Registers (Device 8, Function 3) — Miscellaneous Register

Processor Integrated I/O (IIO) Configuration Registers98 Datasheet, Volume 23.4.2 Standard PCI Configuration Registers3.4.2.1 VID—Vendor Identificatio

Datasheet, Volume 2 99Processor Integrated I/O (IIO) Configuration Registers8RO 0SERR EnableFor PCI Express/DMI ports, this field enables notifying th