Intel LE80538UE0092M Scheda Tecnica

Intel® CoreTM Duo Processor and Intel® CoreTM Solo Processor on 65 nm Process Specification Update June 2009 Revision 020

Summary Tables of Changes 10 Specification Update AK = Intel® Core™2 Extreme quad-core processor QX6000Δ sequence and Intel® Core™2 Quad proce

Summary Tables of Changes Specification Update 11 Stepping Number C0 D0 Dual Core Only Plans ERRATA AE1 X X No Fix FST Instruction with Nu

Summary Tables of Changes 12 Specification Update Stepping Number C0 D0 Dual Core Only Plans ERRATA AE21 X X X No Fix Disable Execution-Disab

Summary Tables of Changes Specification Update 13 Stepping Number C0 D0 Dual Core Only Plans ERRATA AE40 X X No Fix A Write to an APIC Regis

Summary Tables of Changes 14 Specification Update Stepping Number C0 D0 Dual Core Only Plans ERRATA AE60 X X No Fix An Enabled Debug Breakpo

Summary Tables of Changes Specification Update 15 Stepping Number C0 D0 Dual Core Only Plans ERRATA AE81 X X No Fix Store Ordering May be In

Identification Information 16 Specification Update Identification Information Component Identification via Programming Interface The Intel Core

Identification Information Specification Update 17 Table 1. Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process Identificat

Identification Information 18 Specification Update QDF/S-SPEC# Processor # Package Stepping CPUID FSB(MHz) Speed HFM/LFM (GHz) Notes SL92X T140

Errata Specification Update 19 Errata AE1. FST Instruction with Numeric and Null Segment Exceptions May Take Numeric Exception with Incorrect

2 Specification Update INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPL

Errata 20 Specification Update AE4. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Ty

Errata Specification Update 21 AE6. VM Bit Is Cleared on Second Fault Handled by Task Switch from Virtual-8086 (VM86) Problem: Following a ta

Errata 22 Specification Update AE9. LTR Instruction May Result in Unexpected Behavior Problem: Under certain circumstances an LTR (Load Task

Errata Specification Update 23 AE12. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation

Errata 24 Specification Update AE14. MOV to/from Debug Register Causes Debug Exception Problem: When in V86 mode, if a MOV instruction is exe

Errata Specification Update 25 AE17. Machine Check Exception May Occur When Interleaving Code between Different Memory Types Problem: A small

Errata 26 Specification Update AE20. LOCK# Asserted during a Special Cycle Shutdown Transaction May Unexpectedly Deassert Problem: During a p

Errata Specification Update 27 AE24. Disabling of Single-Step On-branch Operation May Be Delayed following a POPFD Instruction Problem: Disab

Errata 28 Specification Update AE27. General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit Proble

Errata Specification Update 29 AE31. Data Breakpoint/Single Step on MOV SS/POP SS May Be Lost after Entry into SMM Problem: Data Breakpoint/S

Specification Update 3 Contents Revision History ...

Errata 30 Specification Update Status: For the steppings affected, see the Summary Tables of Changes.

Errata Specification Update 31 AE34. Pending x87 FPU Exceptions (#MF) following STI May Be Serviced before Higher Priority Interrupts Problem:

Errata 32 Specification Update AE37. The Processor May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (Task-State Segment)

Errata Specification Update 33 AE40. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retir

Errata 34 Specification Update AE42. Simultaneous Access to the Same Page Translation Entries by Both Cores May Lead to Unexpected Processor B

Errata Specification Update 35 AE45. Last Exception Record (LER) MSRs May Be Incorrectly Updated Problem: The LASTINTTOIP and LASTINTFROMIP

Errata 36 Specification Update AE47. Writing the Local Vector Table (LVT) When an Interrupt Is Pending May Cause an Unexpected Interrupt Prob

Errata Specification Update 37 AE49. Counter Enable Bit [22] of IA32_CR_PerfEvtSel0 and IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon (Archit

Errata 38 Specification Update AE51. Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate Problem: The INST_RETIR

Errata Specification Update 39 AE54. SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code (SMC) Event May Cause Unexpected Behavior Pro

Revision History 4 Specification Update Revision History Document Number Revision Description Date 309222 -001 Initial release January 20

Errata 40 Specification Update AE57. Writing Shared Unaligned Data That Crosses a Cache Line without Proper Semaphores or Barriers May Expose

Errata Specification Update 41 AE60. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP SS Instruction if it is Fol

Errata 42 Specification Update Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be used. Workarou

Errata Specification Update 43 AE63. Erratum removed AE64. EFLAGS Discrepancy on Page Faults after a Translation Change Problem: This erratu

Errata 44 Specification Update AE67. Performance Monitoring Event FP_ASSIST May Not Be Accurate Problem: Performance monitoring event FP_ASSI

Errata Specification Update 45 AE69. BTM/BTS Branch-From Instruction Address May Be Incorrect for Software Interrupts Problem: When BTM (Bran

Errata 46 Specification Update AE72. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Problem: The ENTER instruction

Errata Specification Update 47 AE75. Microcode Updates Performed During VMX Non-root Operation Could Result in Unexpected Behavior Problem: W

Errata 48 Specification Update AE77. Page Access Bit May Be Set Prior to Signaling a Code Segment Limit Fault Problem: If code segment limit

Errata Specification Update 49 AE80. An Asynchronous MCE during a Far Transfer May Corrupt ESP Problem: If an asynchronous machine check occu

Revision History Specification Update 5 309222 -014 • Updated Stepping Codes Used in Summary Table • Updated Erratum AE34 • Added Erratum AE

Errata 50 Specification Update stores (referred to as “fast strings”) for optimal performance. FXSAVE may also be internally implemented using

Specification Changes Specification Update 51 Specification Changes There are no specification changes in this specification update revision.

Specification Clarifications 52 Specification Update Specification Clarifications AE2 Enhanced Cache Error Reporting for D0 Stepping Beginning

Documentation Changes Specification Update 53 Documentation Changes There are no documentation changes in this specification update revision. N

Preface 6 Specification Update Preface This document is an update to the specifications contained in the documents listed in the following Affe

Preface Specification Update 7 Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their

Summary Tables of Changes 8 Specification Update Summary Tables of Changes The following table indicates the Specification Changes, Errata, Spe

Summary Tables of Changes Specification Update 9 Note: Each Specification Update item is prefixed with a capital letter to distinguish the pro