Intel 2760QM Scheda Tecnica

Document Number: 326197-001Intel® Core™ i7 Processor Family for the LGA-2011 SocketDatasheet, Volume 2Supporting Desktop Intel® Core™ i7-3960X Extreme

10 Datasheet, Volume 23.3.8.45 VTD1_EXT_CAP—Extended Intel® VT-d Capability Register ...2633.3.8.46 VTD1_GLBCMD—Global Command Register...

Processor Integrated I/O (IIO) Configuration Registers100 Datasheet, Volume 23.2.4.82 RPERRCMD—Root Port Error Command RegisterThis register controls

Datasheet, Volume 2 101Processor Integrated I/O (IIO) Configuration Registers3.2.4.84 ERRSID—Error Source Identification Register4RW1CS 0bFirst Uncor

Processor Integrated I/O (IIO) Configuration Registers102 Datasheet, Volume 23.2.4.85 PERFCTRLSTS—Performance Control and Status RegisterPERFCTRLSTSBu

Datasheet, Volume 2 103Processor Integrated I/O (IIO) Configuration Registers3.2.4.86 MISCCTRLSTS—Miscellaneous Control and Status Register2RW0bEnabl

Processor Integrated I/O (IIO) Configuration Registers104 Datasheet, Volume 237 RW 0bDisable MCTP Broadcast to this link When set, this bit will prev

Datasheet, Volume 2 105Processor Integrated I/O (IIO) Configuration Registers27 RWS 0bSystem Interrupt Only on Link BW/Management Status This bit, w

Processor Integrated I/O (IIO) Configuration Registers106 Datasheet, Volume 211 RWS 1ballow_1nonvc1_after_10vc1s Allow a non-VC1 request from DMI to

Datasheet, Volume 2 107Processor Integrated I/O (IIO) Configuration Registers3.2.4.87 PCIE_IOU_BIF_CTRL—PCIe* Port Bifurcation Control Register – DM

Processor Integrated I/O (IIO) Configuration Registers108 Datasheet, Volume 23.2.4.89 PCIE_IOU_BIF_CTRL—PCIe* Port Bifurcation Control RegisterPCIE_IO

Datasheet, Volume 2 109Processor Integrated I/O (IIO) Configuration Registers3.2.4.90 PXP2CAP—Secondary PCI Express* Extended Capability Header Regi

Datasheet, Volume 2 114.2.2 CSR Register Maps ... 2834.2.3 CBO unicast CSR

Processor Integrated I/O (IIO) Configuration Registers110 Datasheet, Volume 23.2.5 PCI Express* and DMI2 Error RegistersThe architecture model for err

Datasheet, Volume 2 111Processor Integrated I/O (IIO) Configuration Registers3.2.5.3 ERRINJCON—PCI Express* Error Injection Control Register3.2.5.4 C

Processor Integrated I/O (IIO) Configuration Registers112 Datasheet, Volume 23.2.5.5 XPCORERRSTS—XP Correctable Error Status RegisterThe contents of t

Datasheet, Volume 2 113Processor Integrated I/O (IIO) Configuration Registers3.2.5.7 XPUNCERRSTS—XP Uncorrectable Error Status Register3.2.5.8 XPUNCE

Processor Integrated I/O (IIO) Configuration Registers114 Datasheet, Volume 23.2.5.9 XPUNCERRSEV—XP Uncorrectable Error Severity Register3.2.5.10 XPUN

Datasheet, Volume 2 115Processor Integrated I/O (IIO) Configuration Registers3.2.5.11 UNCEDMASK—Uncorrectable Error Detect Status Mask RegisterThis r

Processor Integrated I/O (IIO) Configuration Registers116 Datasheet, Volume 23.2.5.13 RPEDMASK—Root Port Error Detect Status Mask RegisterThis registe

Datasheet, Volume 2 117Processor Integrated I/O (IIO) Configuration Registers3.2.5.15 XPCOREDMASK—XP Correctable Error Detect Mask RegisterThis regis

Processor Integrated I/O (IIO) Configuration Registers118 Datasheet, Volume 23.2.5.17 XPGLBERRPTR—XP Global Error Pointer RegisterCheck that the perfm

Datasheet, Volume 2 119Processor Integrated I/O (IIO) Configuration Registers3.2.5.19 LER_CAP—Live Error Recovery Capability RegisterLive error recov

12 Datasheet, Volume 24.2.5.8 MMCFG_Target_LIST—MMCFG Target List Register ...3354.2.5.9 MMIO_Target_LIST—MMIO Target List Register

Processor Integrated I/O (IIO) Configuration Registers120 Datasheet, Volume 23.2.5.22 LER_UNCERRMSK—Live Error Recovery Uncorrectable Error Mask Regi

Datasheet, Volume 2 121Processor Integrated I/O (IIO) Configuration Registers3.2.5.24 LER_RPERRMSK—Live Error Recovery Root Port Error Mask Register

Processor Integrated I/O (IIO) Configuration Registers122 Datasheet, Volume 23.2.6.2 LN[4:7]EQ—Lane 4 through Lane 7 Equalization Control RegisterThis

Datasheet, Volume 2 123Processor Integrated I/O (IIO) Configuration Registers10:8 RW-O 2hDownstream Component Transmitter Preset Transmitter Preset

Processor Integrated I/O (IIO) Configuration Registers124 Datasheet, Volume 23.2.6.3 LN[8:15]EQ—Lane 8 though Lane 15 Equalization Control RegisterThi

Datasheet, Volume 2 125Processor Integrated I/O (IIO) Configuration Registers3.2.7 PCI Express* and DMI2 Perfmon3.2.7.1 XPPMDL[0:1]—XP PM Data Low Bi

Processor Integrated I/O (IIO) Configuration Registers126 Datasheet, Volume 23.2.7.3 XPPMDH—XP PM Data High Bits RegisterThis register contains the hi

Datasheet, Volume 2 127Processor Integrated I/O (IIO) Configuration Registers3.2.7.5 XPPMR[0:1]—XP PM Response Control RegisterThe PMR register contr

Processor Integrated I/O (IIO) Configuration Registers128 Datasheet, Volume 215:14 RW 00bCount Mode This field sets how the events will be counted.00

Datasheet, Volume 2 129Processor Integrated I/O (IIO) Configuration Registers7:6 RW 00bCompare Mode This field defines how the PMC (compare) registe

Datasheet, Volume 2 134.2.11.8 RIRILV6OFFSET_[0:4]—RIR Range Rank Interleave 6 OFFSET Register...

Processor Integrated I/O (IIO) Configuration Registers130 Datasheet, Volume 23.2.7.6 XPPMEVL[0:1]—XP PM Events Low RegisterSelections in this register

Datasheet, Volume 2 131Processor Integrated I/O (IIO) Configuration Registers27:26 RW 0bRequest or Completion Packet Selection x1 = Request packet1x

Processor Integrated I/O (IIO) Configuration Registers132 Datasheet, Volume 23.2.7.7 XPPMEVH[0:1]—XP PM Events High RegisterSelections in this registe

Datasheet, Volume 2 133Processor Integrated I/O (IIO) Configuration Registers3.2.7.8 XPPMER[0:1]—XP PM Resource Events RegisterThis register is used

Processor Integrated I/O (IIO) Configuration Registers134 Datasheet, Volume 23.2.8 DMI Root Complex Register Block (RCRB)This block is mapped into mem

Datasheet, Volume 2 135Processor Integrated I/O (IIO) Configuration Registers3.2.8.1 DMIVC0RCAP—DMI VC0 Resource Capability Register3.2.8.2 DMIVC0RCT

Processor Integrated I/O (IIO) Configuration Registers136 Datasheet, Volume 23.2.8.3 DMIVC0RSTS—DMI VC0 Resource Status RegisterReports the Virtual Ch

Datasheet, Volume 2 137Processor Integrated I/O (IIO) Configuration Registers3.2.8.5 DMIVC1RCTL—DMI VC1 Resource Control RegisterControls the resourc

Processor Integrated I/O (IIO) Configuration Registers138 Datasheet, Volume 23.2.8.6 DMIVC1RSTS—DMI VC1 Resource Status RegisterReports the Virtual Ch

Datasheet, Volume 2 139Processor Integrated I/O (IIO) Configuration Registers3.2.8.8 DMIVCPRCTL—DMI VCP Resource Control RegisterControls the resourc

14 Datasheet, Volume 24.2.11.39RIRILV5OFFSET_4—RIR Range Rank Interleave 5 OFFSET Register ...

Processor Integrated I/O (IIO) Configuration Registers140 Datasheet, Volume 23.2.8.9 DMIVCPRSTS—DMI VCP Resource Status RegisterReports the Virtual Ch

Datasheet, Volume 2 141Processor Integrated I/O (IIO) Configuration Registers3.2.8.11 DMIVCMRCTL—DMI VCM Resource Control RegisterControls the resour

Processor Integrated I/O (IIO) Configuration Registers142 Datasheet, Volume 23.2.8.13 DMIRCLDECH—DMI Root Complex Link Declaration RegisterThis regist

Datasheet, Volume 2 143Processor Integrated I/O (IIO) Configuration Registers3.2.8.16 DMILBA0—DMI Link Address Register3.2.8.17 DMIVC1CdtThrottle—DMI

Processor Integrated I/O (IIO) Configuration Registers144 Datasheet, Volume 23.2.8.19 DMIVCmCdtThrottle—DMI VCm Credit Throttle RegisterDMIVCmCdtThrot

Datasheet, Volume 2 145Processor Integrated I/O (IIO) Configuration Registers3.3 Integrated I/O Core Registers This section describes the standard PC

Processor Integrated I/O (IIO) Configuration Registers146 Datasheet, Volume 2Table 3-10. Intel® VT-d, Address Map, System Management, Miscellaneous Re

Datasheet, Volume 2 147Processor Integrated I/O (IIO) Configuration RegistersTable 3-11. Intel® VT-d, Address Map, System Management, Miscellaneous R

Processor Integrated I/O (IIO) Configuration Registers148 Datasheet, Volume 2Table 3-12. Intel® VT-d, Address Map, System Management, Miscellaneous Re

Datasheet, Volume 2 149Processor Integrated I/O (IIO) Configuration RegistersTable 3-13. IIO Control/Status and Global Error Register Map – Device 5,

Datasheet, Volume 2 154.2.12.29RIRILV2OFFSET_3—RIR Range Rank Interleave 2 OFFSET Register...

Processor Integrated I/O (IIO) Configuration Registers150 Datasheet, Volume 2Table 3-14. IIO Control/Status and Global Error Register Map – Device 5,

Datasheet, Volume 2 151Processor Integrated I/O (IIO) Configuration RegistersTable 3-15. IIO Local Error Map – Device 5, Function 2 – Offset 200h–2FF

Processor Integrated I/O (IIO) Configuration Registers152 Datasheet, Volume 2Table 3-16. IIO Local Error Map – Device 5, Function 2 – Offset 300h–3FFh

Datasheet, Volume 2 153Processor Integrated I/O (IIO) Configuration RegistersTable 3-17. I/OxAPIC PCI Configuration Space Map – Device 5/Function 4 –

Processor Integrated I/O (IIO) Configuration Registers154 Datasheet, Volume 2Table 3-18. I/OxAPIC PCI Configuration Space Map – Device 5/Function 4 –

Datasheet, Volume 2 155Processor Integrated I/O (IIO) Configuration Registers3.3.2 PCI Configuration Space Registers Common to Device 53.3.2.1 VID—Ve

Processor Integrated I/O (IIO) Configuration Registers156 Datasheet, Volume 23.3.2.4 PCISTS—PCI Status RegisterThe PCI Status register is a 16-bit sta

Datasheet, Volume 2 157Processor Integrated I/O (IIO) Configuration Registers3.3.2.5 RID—Revision Identification RegisterThis register contains the r

Processor Integrated I/O (IIO) Configuration Registers158 Datasheet, Volume 23.3.2.8 HDR—Header Type RegisterThis register identifies the header layou

Datasheet, Volume 2 159Processor Integrated I/O (IIO) Configuration Registers3.3.2.11 CAPPTR—Capability Pointer RegisterThe CAPPTR provides the offse

16 Datasheet, Volume 24.2.14.2 TCRAP—Timing Constraints DDR3 Regular Access Parameter Register...

Processor Integrated I/O (IIO) Configuration Registers160 Datasheet, Volume 23.3.2.15 PXPNXTPTR—PCI Express* Next Pointer Register The PCI Express Cap

Datasheet, Volume 2 161Processor Integrated I/O (IIO) Configuration Registers3.3.3.2 MMCFG—MMCFG Address Range Register3.3.3.3 TSEG—TSeg Address Rang

Processor Integrated I/O (IIO) Configuration Registers162 Datasheet, Volume 23.3.3.5 GENPROTRANGE1_LIMIT—Generic Protected Memory Range 1 Limit Addre

Datasheet, Volume 2 163Processor Integrated I/O (IIO) Configuration Registers3.3.3.7 GENPROTRANGE2_LIMIT—Generic Protected Memory Range 2 Limit Addr

Processor Integrated I/O (IIO) Configuration Registers164 Datasheet, Volume 23.3.3.10 NCMEM_BASE—NCMEM Base Register3.3.3.11 NCMEM_LIMIT—NCMEM Limit R

Datasheet, Volume 2 165Processor Integrated I/O (IIO) Configuration Registers3.3.3.13 MENCMEM_LIMIT—Intel® ME Non-coherent Memory Limit Address Regi

Processor Integrated I/O (IIO) Configuration Registers166 Datasheet, Volume 23.3.3.15 LMMIOL—Local MMIO Low Base Register3.3.3.16 LMMIOH_BASE—Local MM

Datasheet, Volume 2 167Processor Integrated I/O (IIO) Configuration Registers3.3.3.17 LMMIOH_LIMIT—Local MMIO High Base Register3.3.3.18 GENPROTRANGE

Processor Integrated I/O (IIO) Configuration Registers168 Datasheet, Volume 23.3.3.19 GENPROTRANGE0_LIMIT—Generic Protected Memory Range 0 Limit Addr

Datasheet, Volume 2 169Processor Integrated I/O (IIO) Configuration Registers11:9 RW 0hRRB Size (Write Cache Size) Specifies the number of entries u

Datasheet, Volume 2 174.2.16.10CORRERRCNT_2—Corrected Error Count Register... 4494.2.16.11CORRERRCNT_3—Corrected Error Count Regi

Processor Integrated I/O (IIO) Configuration Registers170 Datasheet, Volume 23.3.3.21 CIPSTS—Coherent Interface Protocol Status Register3.3.3.22 CIPDC

Datasheet, Volume 2 171Processor Integrated I/O (IIO) Configuration Registers3.3.3.23 CIPINTRC—Coherent Interface Protocol Interrupt Control Register

Processor Integrated I/O (IIO) Configuration Registers172 Datasheet, Volume 23.3.3.24 CIPINTRS—Coherent interface Protocol Interrupt Status RegisterTh

Datasheet, Volume 2 173Processor Integrated I/O (IIO) Configuration Registers3.3.3.25 VTBAR—Base Address Register for Intel® VT-d Registers3.3.3.26 V

Processor Integrated I/O (IIO) Configuration Registers174 Datasheet, Volume 23.3.3.27 VTISOCHCTRL—Intel® VT-d Isoch Related Control RegisterVTISOCHCTR

Datasheet, Volume 2 175Processor Integrated I/O (IIO) Configuration Registers3.3.3.28 VTGENCTRL2—Intel® VT-d General Control 2 RegisterVTGENCTRL2Bus:

Processor Integrated I/O (IIO) Configuration Registers176 Datasheet, Volume 23.3.3.29 IOTLBPARTITION—IOTLB Partitioning Control Register3.3.3.30 VTUNC

Datasheet, Volume 2 177Processor Integrated I/O (IIO) Configuration Registers3.3.3.31 VTUNCERRMSK—Intel® VT Uncorrectable Error Mask Register3.3.3.32

Processor Integrated I/O (IIO) Configuration Registers178 Datasheet, Volume 23.3.3.33 VTUNCERRPTR—Intel® VT Uncorrectable Error Pointer Register3.3.3.

Datasheet, Volume 2 179Processor Integrated I/O (IIO) Configuration Registers36:35 RV 0h Reserved 34:32 RWS 000bShow the PCI Express Port identifier

18 Datasheet, Volume 24.4.2.20 PRIP_TURBO_PWR_LIM—Primary Plane Turbo Power Limitation Register ...

Processor Integrated I/O (IIO) Configuration Registers180 Datasheet, Volume 224 RW 0bDisable all allocating flows When this bit is set, IIO will no m

Datasheet, Volume 2 181Processor Integrated I/O (IIO) Configuration Registers14 RW 0bPipeline Non-Snooped Writes on the Coherent Interface When this

Processor Integrated I/O (IIO) Configuration Registers182 Datasheet, Volume 23.3.3.35 IRP_MISC_DFX0—Coherent Interface Miscellaneous DFx 0 RegisterIR

Datasheet, Volume 2 183Processor Integrated I/O (IIO) Configuration Registers3.3.3.36 IRP_MISC_DFX1—Coherent Interface Miscellaneous DFx 1 Register1

Processor Integrated I/O (IIO) Configuration Registers184 Datasheet, Volume 23.3.3.37 IRP0DELS—Coherent Interface 0 Debug Event Lane Select Register3

Datasheet, Volume 2 185Processor Integrated I/O (IIO) Configuration Registers3.3.3.39 IRP0DBGRING[0:1]—Coherent Interface 0 Debug Ring 0 Register3.3.

Processor Integrated I/O (IIO) Configuration Registers186 Datasheet, Volume 23.3.3.43 IRP0RNG—Coherent Interface 0 Cluster Debug Ring Control Registe

Datasheet, Volume 2 187Processor Integrated I/O (IIO) Configuration Registers14:12 RWS-L 000bDebug ring source lane 4 select This field selects the

Processor Integrated I/O (IIO) Configuration Registers188 Datasheet, Volume 23.3.3.44 IRP1RNG—Coherent Interface 1 Cluster Debug Ring Control Registe

Datasheet, Volume 2 189Processor Integrated I/O (IIO) Configuration Registers14:12 RWS-L 000bDebug ring source lane 4 select This field selects the

Datasheet, Volume 2 194.5.2.7 UBOXErrSts—Error Status Register... 5224.5.2.8 EVENTS_DEBUG Register...

Processor Integrated I/O (IIO) Configuration Registers190 Datasheet, Volume 23.3.3.45 IRPEGCREDITS—R2PCIe Egress Credits RegisterThis register specifi

Datasheet, Volume 2 191Processor Integrated I/O (IIO) Configuration Registers3.3.4 Global System Control and Error Registers3.3.4.1 IRPPERRSV—IRP Pro

Processor Integrated I/O (IIO) Configuration Registers192 Datasheet, Volume 23.3.4.2 IIOERRSV—IIO Core Error Severity RegisterThis register associates

Datasheet, Volume 2 193Processor Integrated I/O (IIO) Configuration Registers3.3.4.4 PCIERRSV—PCIe* Error Severity Map RegisterThis register allows r

Processor Integrated I/O (IIO) Configuration Registers194 Datasheet, Volume 23.3.4.6 VIRAL—Viral Alert RegisterThis register provides the option to ge

Datasheet, Volume 2 195Processor Integrated I/O (IIO) Configuration Registers3.3.4.8 ERRPINST—Error Pin Status RegisterThis register reflects the sta

Processor Integrated I/O (IIO) Configuration Registers196 Datasheet, Volume 23.3.4.10 VPPCTL—VPP Control RegisterThis register defines the control/com

Datasheet, Volume 2 197Processor Integrated I/O (IIO) Configuration Registers3.3.4.12 GNERRST—Global Non-Fatal Error Status RegisterThis register ind

Processor Integrated I/O (IIO) Configuration Registers198 Datasheet, Volume 23.3.4.13 GFERRST—Global Fatal Error Status RegisterThis register indicate

Datasheet, Volume 2 199Processor Integrated I/O (IIO) Configuration Registers3.3.4.14 GERRCTL—Global Error Control RegisterThis register controls/mas

2 Datasheet, Volume 2Legal Lines and Disclaimersal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. N

20 Datasheet, Volume 24.8.7 DDRIOTXTopRank0A[0:1]—DDRIOTXTopRank0 Register...5474.8.8 DDRIOCtlPICode0A[0:1]—DDRIOCtlPICode0 R

Processor Integrated I/O (IIO) Configuration Registers200 Datasheet, Volume 23.3.4.15 GSYSST—Global System Event Status RegisterThis register indicate

Datasheet, Volume 2 201Processor Integrated I/O (IIO) Configuration Registers3.3.4.18 GFNERRST—Global Fatal NERR Status Register3.3.4.19 GNFERRST—Glo

Processor Integrated I/O (IIO) Configuration Registers202 Datasheet, Volume 23.3.5 Local Error Registers3.3.5.1 IRPP0ERRST—IRP Protocol Error Status R

Datasheet, Volume 2 203Processor Integrated I/O (IIO) Configuration Registers3.3.5.3 IRPP0FFERRST—IRP Protocol Fatal FERR Status RegisterThe error st

Processor Integrated I/O (IIO) Configuration Registers204 Datasheet, Volume 23.3.5.4 IRPP0FNERRST—IRP Protocol Fatal NERR Status RegisterThe error sta

Datasheet, Volume 2 205Processor Integrated I/O (IIO) Configuration Registers3.3.5.6 IRPP0NFERRST—IRP Protocol Non-Fatal FERR Status RegisterThe erro

Processor Integrated I/O (IIO) Configuration Registers206 Datasheet, Volume 23.3.5.8 IRPP0NFERRHD[0:3]—IRP Protocol Non-Fatal FERR Header Log 0 Regis

Datasheet, Volume 2 207Processor Integrated I/O (IIO) Configuration Registers3.3.5.11 IRPP1ERRST—IRP Protocol Error Status RegisterThis register indi

Processor Integrated I/O (IIO) Configuration Registers208 Datasheet, Volume 23.3.5.12 IRPP1ERRCTL—IRP Protocol Error Control RegisterThis register ena

Datasheet, Volume 2 209Processor Integrated I/O (IIO) Configuration Registers3.3.5.13 IRPP1FFERRST—IRP Protocol Fatal FERR Status RegisterThe error s

Datasheet, Volume 2 213-7 Device 0/Function 0 DMI2 mode), Devices 2/Functions 0 (PCIe* Root Port),and Device 3/Function 0 (PCIe* Root Port) Extended

Processor Integrated I/O (IIO) Configuration Registers210 Datasheet, Volume 23.3.5.15 IRPP1FFERRHD[0:3]—IRP Protocol Fatal FERR Header Log 0 Register

Datasheet, Volume 2 211Processor Integrated I/O (IIO) Configuration Registers3.3.5.17 IRPP1NNERRST—IRP Protocol Non-Fatal NERR Status RegisterThe err

Processor Integrated I/O (IIO) Configuration Registers212 Datasheet, Volume 23.3.5.20 IRPP1ERRCNT—IRP Protocol Error Counter Register3.3.5.21 IIOERRST

Datasheet, Volume 2 213Processor Integrated I/O (IIO) Configuration Registers3.3.5.23 IIOFFERRST—IIO Core Fatal FERR Status Register3.3.5.24 IIOFFERR

Processor Integrated I/O (IIO) Configuration Registers214 Datasheet, Volume 23.3.5.27 IIONFERRHD[0:3]—IIO Core Non-Fatal FERR Header RegisterHeader lo

Datasheet, Volume 2 215Processor Integrated I/O (IIO) Configuration Registers3.3.5.30 IIOERRCNT—IIO Core Error Counter Register3.3.5.31 MIERRST—Misce

Processor Integrated I/O (IIO) Configuration Registers216 Datasheet, Volume 23.3.5.33 MIFFERRST—Miscellaneous Fatal First Error Status Register3.3.5.3

Datasheet, Volume 2 217Processor Integrated I/O (IIO) Configuration Registers3.3.5.37 MINFERRHDR_[0:3]—Miscellaneous Non-Fatal First Error Header 0

Processor Integrated I/O (IIO) Configuration Registers218 Datasheet, Volume 23.3.6 IOxAPIC PCI Configuration SpaceThis section covers the I/OxAPIC rel

Datasheet, Volume 2 219Processor Integrated I/O (IIO) Configuration Registers3.3.6.4 INTL—Interrupt Line Register3.3.6.5 INTPIN—Interrupt Pin Registe

22 Datasheet, Volume 2Function 4, Offset 00h–FChMemory Controller Channel 1 Thermal Control Registers: Bus N, Device 16,Function 5, Offset 00h–FCh..

Processor Integrated I/O (IIO) Configuration Registers220 Datasheet, Volume 23.3.6.7 PMCAP—Power Management Capabilities Register3.3.6.8 PMCSR—Power M

Datasheet, Volume 2 221Processor Integrated I/O (IIO) Configuration Registers3.3.6.9 RDINDEX—Alternate Index to read Indirect I/OxAPIC Register3.3.6.

Processor Integrated I/O (IIO) Configuration Registers222 Datasheet, Volume 23.3.6.11 IOAPICTETPC—IOxAPIC Table Entry Target Programmable Control Reg

Datasheet, Volume 2 223Processor Integrated I/O (IIO) Configuration Registers3.3.6.13 IOADSELS1—IOxAPIC DSELS Register 13.3.6.14 IOINTSRC0—IO Interru

Processor Integrated I/O (IIO) Configuration Registers224 Datasheet, Volume 23.3.6.15 IOINTSRC1—IO Interrupt Source Register 13.3.6.16 IOREMINTCNT—Rem

Datasheet, Volume 2 225Processor Integrated I/O (IIO) Configuration Registers3.3.6.17 IOREMGPECNT—Remote IO GPE Count Register3.3.6.18 IOXAPICPARERRI

Processor Integrated I/O (IIO) Configuration Registers226 Datasheet, Volume 23.3.7 I/OxAPIC Memory Mapped RegistersI/OxAPIC has a direct memory mapped

Datasheet, Volume 2 227Processor Integrated I/O (IIO) Configuration RegistersTable 3-20. I/OxAPIC Indexed Registers (Redirection Table Entries) – WIN

Processor Integrated I/O (IIO) Configuration Registers228 Datasheet, Volume 23.3.7.1 INDX—Index RegisterThe Index Register will select which indirect

Datasheet, Volume 2 229Processor Integrated I/O (IIO) Configuration Registers3.3.7.4 EOI Register3.3.7.5 APICID RegisterThis register uniquely identi

Datasheet, Volume 2 23Offset 200h–2FChMemory Controller Channel 1 Error Registers: Bus N, Device 16, Function 7,Offset 200h–2FCh ...

Processor Integrated I/O (IIO) Configuration Registers230 Datasheet, Volume 23.3.7.7 ARBID—Arbitration ID RegisterThis is a legacy register carried ov

Datasheet, Volume 2 231Processor Integrated I/O (IIO) Configuration Registers3.3.7.9 RTL[0:23]—Redirection Table Low DWord RegisterThe information in

Processor Integrated I/O (IIO) Configuration Registers232 Datasheet, Volume 23.3.7.10 RTH[0:23]—Redirection Table High DWord Register12 RO 0bDelivery

Datasheet, Volume 2 233Processor Integrated I/O (IIO) Configuration Registers3.3.8 Intel® VT-d Memory Mapped RegisterIntel VT-d registers are all add

Processor Integrated I/O (IIO) Configuration Registers234 Datasheet, Volume 2Table 3-21. Intel® VT-d Memory Mapped Registers – 00h–FFh (VTD0)VTD0_VERS

Datasheet, Volume 2 235Processor Integrated I/O (IIO) Configuration RegistersTable 3-22. Intel® VT-d Memory Mapped Registers – 100h–1FCh (VTD0)VTD0_F

Processor Integrated I/O (IIO) Configuration Registers236 Datasheet, Volume 2Table 3-23. Intel® VT-d Memory Mapped Registers – 200h–2FCh (VTD0), 1200h

Datasheet, Volume 2 237Processor Integrated I/O (IIO) Configuration RegistersTable 3-24. Intel® VT-d Memory Mapped Registers – 1000h–11FCh (VTD1) VT

Processor Integrated I/O (IIO) Configuration Registers238 Datasheet, Volume 2Table 3-25. Intel® VT-d Memory Mapped Registers – 1100h–11FCh (VTD1) VTD

Datasheet, Volume 2 239Processor Integrated I/O (IIO) Configuration Registers3.3.8.1 VTD0_VERSION—Version Number Register3.3.8.2 VTD0_CAP—Intel® VT-d

24 Datasheet, Volume 2Revision History§Revision NumberDescription Date001 • Initial release November 2011002 • Updated to clarify references to PCI Ex

Processor Integrated I/O (IIO) Configuration Registers240 Datasheet, Volume 23.3.8.3 VTD0_EXT_CAP—Extended Intel® VT-d Capability Register7RO0bCM The

Datasheet, Volume 2 241Processor Integrated I/O (IIO) Configuration Registers3.3.8.4 VTD0_GLBCMD—Global Command Register1RWO 1bQueued Invalidation Su

Processor Integrated I/O (IIO) Configuration Registers242 Datasheet, Volume 227 RO 0bWrite Buffer Flush Not Applicable to the processor 26 RW 0bQueue

Datasheet, Volume 2 243Processor Integrated I/O (IIO) Configuration Registers3.3.8.5 VTD0_GLBSTS—Global Status Register23 RW 0bCompatibility Format I

Processor Integrated I/O (IIO) Configuration Registers244 Datasheet, Volume 23.3.8.6 VTD0_ROOTENTRYADD—Root Entry Table Address Register3.3.8.7 VTD0_C

Datasheet, Volume 2 245Processor Integrated I/O (IIO) Configuration Registers62:61 RW 0bContext Invalidation Request Granularity When requesting har

Processor Integrated I/O (IIO) Configuration Registers246 Datasheet, Volume 23.3.8.8 VTD0_FLTSTS—Fault Status RegisterVTD0_FLTSTSBus: 0 Device: 5 Func

Datasheet, Volume 2 247Processor Integrated I/O (IIO) Configuration Registers3.3.8.9 VTD0_FLTEVTCTRL—Fault Event Control Register3.3.8.10 VTD0_FLTEVT

Processor Integrated I/O (IIO) Configuration Registers248 Datasheet, Volume 23.3.8.11 VTD0_FLTEVTADDR—Fault Event Address Register3.3.8.12 VTD0_PMEN—P

Datasheet, Volume 2 249Processor Integrated I/O (IIO) Configuration Registers3.3.8.14 VTD0_PROT_LOW_MEM_LIMIT—Protected Memory Low Limit Register3.3

Datasheet, Volume 2 25Introduction1 IntroductionThis document is Volume 2 of the datasheet for the Intel® Core™ i7 processor family for the LGA-2011

Processor Integrated I/O (IIO) Configuration Registers250 Datasheet, Volume 23.3.8.17 VTD0_INV_QUEUE_HEAD—Invalidation Queue Header Pointer Register3

Datasheet, Volume 2 251Processor Integrated I/O (IIO) Configuration Registers3.3.8.20 VTD0_INV_COMP_STATUS—Invalidation Completion Status Register3.

Processor Integrated I/O (IIO) Configuration Registers252 Datasheet, Volume 23.3.8.22 VTD0_INV_COMP_EVT_DATA—Invalidation Completion Event Data Regis

Datasheet, Volume 2 253Processor Integrated I/O (IIO) Configuration Registers3.3.8.25 VTD0_FLTREC0_GPA—Fault Record Register3.3.8.26 VTD0_FLTREC0_SRC

Processor Integrated I/O (IIO) Configuration Registers254 Datasheet, Volume 23.3.8.28 VTD0_FLTREC1_SRC—Fault Record Register3.3.8.29 VTD0_FLTREC2_GPA—

Datasheet, Volume 2 255Processor Integrated I/O (IIO) Configuration Registers3.3.8.30 VTD0_FLTREC2_SRC—Fault Record Register3.3.8.31 VTD0_FLTREC3_GPA

Processor Integrated I/O (IIO) Configuration Registers256 Datasheet, Volume 23.3.8.32 VTD0_FLTREC3_SRC—Fault Record Register3.3.8.33 VTD0_FLTREC4_GPA—

Datasheet, Volume 2 257Processor Integrated I/O (IIO) Configuration Registers3.3.8.34 VTD0_FLTREC4_SRC—Fault Record Register3.3.8.35 VTD0_FLTREC5_GPA

Processor Integrated I/O (IIO) Configuration Registers258 Datasheet, Volume 23.3.8.36 VTD0_FLTREC5_SRC—Fault Record Register3.3.8.37 VTD0_FLTREC6_GPA—

Datasheet, Volume 2 259Processor Integrated I/O (IIO) Configuration Registers3.3.8.38 VTD0_FLTREC6_SRC—Fault Record Register3.3.8.39 VTD0_FLTREC7_GPA

Introduction26 Datasheet, Volume 2Execute Disable BitThe Execute Disable bit allows memory to be marked as executable or non-executable, when combined

Processor Integrated I/O (IIO) Configuration Registers260 Datasheet, Volume 23.3.8.40 VTD0_FLTREC7_SRC—Fault Record Register3.3.8.41 VTD0_INVADDRREG—I

Datasheet, Volume 2 261Processor Integrated I/O (IIO) Configuration Registers3.3.8.42 VTD0_IOTLBINV—IOTLB Invalidate RegisterVTD0_IOTLBINVBus: 0 Devi

Processor Integrated I/O (IIO) Configuration Registers262 Datasheet, Volume 23.3.8.43 VTD1_VERSION—Version Number Register3.3.8.44 VTD1_CAP—Intel® VT-

Datasheet, Volume 2 263Processor Integrated I/O (IIO) Configuration Registers3.3.8.45 VTD1_EXT_CAP—Extended Intel® VT-d Capability Register6RO 1bPHMR

Processor Integrated I/O (IIO) Configuration Registers264 Datasheet, Volume 23.3.8.46 VTD1_GLBCMD—Global Command RegisterVTD1_GLBCMDBus: 0 Device: 5 F

Datasheet, Volume 2 265Processor Integrated I/O (IIO) Configuration Registers25 RW 0bInterrupt Remapping Enable 0 = Disable Interrupt Remapping Hard

Processor Integrated I/O (IIO) Configuration Registers266 Datasheet, Volume 23.3.8.47 VTD1_GLBSTS—Global Status Register3.3.8.48 VTD1_ROOTENTRYADD—Roo

Datasheet, Volume 2 267Processor Integrated I/O (IIO) Configuration Registers3.3.8.49 VTD1_CTXCMD—Context Command RegisterVTD1_CTXCMDBus: 0 Device: 5

Processor Integrated I/O (IIO) Configuration Registers268 Datasheet, Volume 23.3.8.50 VTD1_FLTSTS—Fault Status RegisterVTD1_FLTSTSBus: 0 Device: 5 Fun

Datasheet, Volume 2 269Processor Integrated I/O (IIO) Configuration Registers3.3.8.51 VTD1_FLTEVTCTRL—Fault Event Control Register3.3.8.52 VTD1_FLTEV

Datasheet, Volume 2 27Introduction1.2 Related DocumentsRefer to the following documents for additional information.SMBusSystem Management Bus. A two-

Processor Integrated I/O (IIO) Configuration Registers270 Datasheet, Volume 23.3.8.53 VTD1_FLTEVTADDR—Fault Event Address Register3.3.8.54 VTD1_PMEN—P

Datasheet, Volume 2 271Processor Integrated I/O (IIO) Configuration Registers3.3.8.56 VTD1_PROT_LOW_MEM_LIMIT—Protected Memory Low Limit Register3.3

Processor Integrated I/O (IIO) Configuration Registers272 Datasheet, Volume 23.3.8.59 VTD1_INV_QUEUE_HEAD—Invalidation Queue Header Pointer Register3

Datasheet, Volume 2 273Processor Integrated I/O (IIO) Configuration Registers3.3.8.62 VTD1_INV_COMP_STATUS—Invalidation Completion Status Register3.

Processor Integrated I/O (IIO) Configuration Registers274 Datasheet, Volume 23.3.8.65 VTD1_INV_COMP_EVT_ADDR—Invalidation Completion Event Address Re

Datasheet, Volume 2 275Processor Integrated I/O (IIO) Configuration Registers3.3.8.68 VTD1_FLTREC0_SRC—Fault Record Register3.3.8.69 VTD1_INVADDRREG—

Processor Integrated I/O (IIO) Configuration Registers276 Datasheet, Volume 23.3.8.70 VTD1_IOTLBINV—IOTLB Invalidate Register§VTD1_IOTLBINVBus: 0 Devi

Datasheet, Volume 2 277Processor Uncore Configuration Registers4 Processor Uncore Configuration RegistersThis chapter also contains the Integrated Me

Processor Uncore Configuration Registers278 Datasheet, Volume 24.1.3 PCICMD—PCI Command RegisterPCICMDOffset: 4hBit AttrReset ValueDescription15:11 RV

Datasheet, Volume 2 279Processor Uncore Configuration Registers4.1.4 PCISTS—PCI Status RegisterPCISTSOffset: 6hBit AttrReset ValueDescription15 RO 0b

Introduction28 Datasheet, Volume 21.3 Register TerminologyThe bits in configuration register descriptions will have an assigned attribute from Table 1

Processor Uncore Configuration Registers280 Datasheet, Volume 24.1.5 RID—Revision Identification Register4.1.6 CCR—Class Code Register4.1.7 CLSR—Cache

Datasheet, Volume 2 281Processor Uncore Configuration Registers4.1.9 HDR—Header Type Register4.1.10 BIST—Built-In Self Test Register4.1.11 SVID—Subsy

Processor Uncore Configuration Registers282 Datasheet, Volume 24.1.13 CAPPTR—Capability Pointer Register4.1.14 INTL—Interrupt Line Register4.1.15 INTP

Datasheet, Volume 2 283Processor Uncore Configuration Registers4.2 Integrated Memory Controller Configuration RegistersThe Integrated Memory Controll

Processor Uncore Configuration Registers284 Datasheet, Volume 2Table 4-2. System Address Decoder (CBo) : Device 12, Function 6, Offset 00h–FCh DID VI

Datasheet, Volume 2 285Processor Uncore Configuration RegistersTable 4-3. Caching agent broadcast registers(CBo) : Device 12, Function 7, Offset 00h

Processor Uncore Configuration Registers286 Datasheet, Volume 2Table 4-4. Caching agent broadcast registers(CBo): Device 13, Function 6, Offset 00h–F

Datasheet, Volume 2 287Processor Uncore Configuration RegistersTable 4-5. Memory Controller Target Address Decoder Registers: Device 15, Function 0,

Processor Uncore Configuration Registers288 Datasheet, Volume 2Table 4-6. Memory Controller MemHot and SMBus Registers: Bus N, Device 15, Function 0,

Datasheet, Volume 2 289Processor Uncore Configuration RegistersTable 4-7. Memory Controller RAS Registers: Bus N, Device 15, Function 1, Offset 00h–

Datasheet, Volume 2 29Introduction§RW-LBRead/Write Lock Bypass : Similar to RWL, these bits can be read and written by software. HW can make these bi

Processor Uncore Configuration Registers290 Datasheet, Volume 2Table 4-8. Memory Controller RAS Registers: Bus N, Device 15, Function 1, Offset 100h–

Datasheet, Volume 2 291Processor Uncore Configuration RegistersTable 4-9. Memory Controller DIMM Timing and Interleave Registers: Bus N, Device 15,

Processor Uncore Configuration Registers292 Datasheet, Volume 2The following register maps are for memory controller control logic registers:Table 4-1

Datasheet, Volume 2 293Processor Uncore Configuration RegistersTable 4-11. Memory Controller Channel 2 Thermal Control Registers: Bus N, Device 16,F

Processor Uncore Configuration Registers294 Datasheet, Volume 2.Table 4-12. Memory Controller Channel 2 Thermal Control Registers: Bus N, Device 16,F

Datasheet, Volume 2 295Processor Uncore Configuration RegistersTable 4-13. Memory Controller Channel 2 DIMM Timing Registers: Bus N, Device 16,Funct

Processor Uncore Configuration Registers296 Datasheet, Volume 2Table 4-14. Memory Controller Channel 2 DIMM Timing Registers: Bus N, Device 16,Functi

Datasheet, Volume 2 297Processor Uncore Configuration RegistersTable 4-15. Memory Controller Channel 2 DIMM Training Registers: Bus N, Device 16,Fun

Processor Uncore Configuration Registers298 Datasheet, Volume 2Table 4-16. Memory Controller Channel 2 Error Registers: Bus N, Device 16, Function 2,

Datasheet, Volume 2 299Processor Uncore Configuration RegistersTable 4-17. Memory Controller Channel 2 Error Registers: Bus N, Device 16, Function 2,

Datasheet, Volume 2 3Contents1Introduction...

Introduction30 Datasheet, Volume 2

Processor Uncore Configuration Registers300 Datasheet, Volume 2Table 4-18. Memory Controller Channel 2 Error Registers: Bus N, Device 16, Function 2,

Datasheet, Volume 2 301Processor Uncore Configuration Registers4.2.3 CBO unicast CSRs4.2.3.1 RTID_Config_Pool01_Size—Ring Global Configuration Regist

Processor Uncore Configuration Registers302 Datasheet, Volume 24.2.3.3 RTID_Config_Pool45_Size—Ring Global Configuration RegisterThis control register

Datasheet, Volume 2 303Processor Uncore Configuration Registers4.2.3.5 VNA_Credit_Config—VNA Credit Configuration RegisterRegister related to VNA Cre

Processor Uncore Configuration Registers304 Datasheet, Volume 24.2.3.7 PipeDbgBusSel—Pipe Debug Bus Select RegisterPipe Debug Bus Select 4.2.3.8 SadDb

Datasheet, Volume 2 305Processor Uncore Configuration Registers4.2.3.10 CBO_GDXC_PKT_CNTRL—CBO GDXC Packet Control RegisterThis register is controlle

Processor Uncore Configuration Registers306 Datasheet, Volume 24.2.3.11 RTID_Config_Pool01_Base—Ring Global Configuration RegisterThis control registe

Datasheet, Volume 2 307Processor Uncore Configuration Registers4.2.3.12 RTID_Config_Pool23_Base—Ring Global Configuration RegisterThis control regist

Processor Uncore Configuration Registers308 Datasheet, Volume 24.2.3.13 RTID_Config_Pool45_Base—Ring Global Configuration RegisterThis control registe

Datasheet, Volume 2 309Processor Uncore Configuration Registers4.2.3.14 RTID_Config_Pool67_Base—Ring Global Configuration RegisterThis control regist

Datasheet, Volume 2 31Configuration Process and Registers2 Configuration Process and Registers2.1 Platform Configuration StructureThe DMI2 physically

Processor Uncore Configuration Registers310 Datasheet, Volume 24.2.3.15 RTID_Pool_Config—Ring Global Configuration RegisterThis control register conta

Datasheet, Volume 2 311Processor Uncore Configuration Registers4.2.3.16 RTID_Config_Pool01_Base_Shadow—Ring Global Configuration Shadow RegisterThis

Processor Uncore Configuration Registers312 Datasheet, Volume 24.2.3.17 RTID_Config_Pool23_Base_Shadow—Ring Global Configuration Shadow RegisterThis

Datasheet, Volume 2 313Processor Uncore Configuration Registers4.2.3.18 RTID_Config_Pool45_Base_Shadow—Ring Global Configuration Shadow RegisterThis

Processor Uncore Configuration Registers314 Datasheet, Volume 24.2.3.19 RTID_Config_Pool67_Base_Shadow—Ring Global Configuration Shadow RegisterThis

Datasheet, Volume 2 315Processor Uncore Configuration Registers4.2.3.20 RTID_Pool_Config_Shadow— Ring Global Configuration Shadow RegisterThis contr

Processor Uncore Configuration Registers316 Datasheet, Volume 24.2.4 System Address Decoder Registers (CBO)4.2.4.1 PAM0123—CBO SAD PAM RegisterPAM0123

Datasheet, Volume 2 317Processor Uncore Configuration Registers4.2.4.2 PAM456—CBO SAD PAM Register9:8 RW 0hPAM1_LOENABLE: 0C0000h-0C3FFFh Attribute (

Processor Uncore Configuration Registers318 Datasheet, Volume 29:8 RW 0hPAM5_LOENABLE: 0E0000h-0E3FFFh Attribute (LOENABLE) This field controls the st

Datasheet, Volume 2 319Processor Uncore Configuration Registers4.2.4.3 SMRAMC—System Management RAM Control RegisterSMRAMCBus: 1 Device: 12 Function:

Configuration Process and Registers32 Datasheet, Volume 2also contains the extended PCI Express configuration space that include PCI Express error sta

Processor Uncore Configuration Registers320 Datasheet, Volume 24.2.4.4 MESEG_BASE—Manageability Engine Base Address Register4.2.4.5 MESEG_LIMIT—Manage

Datasheet, Volume 2 321Processor Uncore Configuration Registers4.2.4.6 DRAM_RULE[0:9]—DRAM Rule 0 Register4.2.4.7 INTERLEAVE_LIST[0:9]—DRAM Interleav

Processor Uncore Configuration Registers322 Datasheet, Volume 24.2.4.8 DRAM_RULE_1—DRAM Rule 1 Register4.2.4.9 INTERLEAVE_LIST_1—DRAM Interleave List

Datasheet, Volume 2 323Processor Uncore Configuration Registers4.2.4.10 DRAM_RULE_2—DRAM Rule 2 Register4.2.4.11 INTERLEAVE_LIST_2—DRAM Interleave Li

Processor Uncore Configuration Registers324 Datasheet, Volume 24.2.4.12 DRAM_RULE_3—DRAM Rule 3 Register4.2.4.13 INTERLEAVE_LIST_3—DRAM Interleave Lis

Datasheet, Volume 2 325Processor Uncore Configuration Registers4.2.4.14 DRAM_RULE_4—DRAM Rule 4 Register4.2.4.15 INTERLEAVE_LIST_4—DRAM Interleave Li

Processor Uncore Configuration Registers326 Datasheet, Volume 24.2.4.16 DRAM_RULE_5—DRAM Rule 5 Register4.2.4.17 INTERLEAVE_LIST_5—DRAM Interleave Lis

Datasheet, Volume 2 327Processor Uncore Configuration Registers4.2.4.18 DRAM_RULE_6—DRAM Rule 6 Register4.2.4.19 INTERLEAVE_LIST_6—DRAM Interleave Li

Processor Uncore Configuration Registers328 Datasheet, Volume 24.2.4.20 DRAM_RULE_7—DRAM Rule 7 Register4.2.4.21 INTERLEAVE_LIST_7—DRAM Interleave Lis

Datasheet, Volume 2 329Processor Uncore Configuration Registers4.2.4.22 DRAM_RULE_8—DRAM Rule 8 Register4.2.4.23 INTERLEAVE_LIST_8—DRAM Interleave Li

Datasheet, Volume 2 33Configuration Process and Registers2.1.2 Processor Uncore Devices (CPUBUSN0 (1))The configuration registers for these devices a

Processor Uncore Configuration Registers330 Datasheet, Volume 24.2.4.24 DRAM_RULE_9—DRAM Rule 9 Register4.2.4.25 INTERLEAVE_LIST_9—DRAM Interleave Lis

Datasheet, Volume 2 331Processor Uncore Configuration Registers4.2.5 Caching Agent Broadcast Registers (CBo)4.2.5.1 Cbo_ISOC_Config—Cbo Isochrony Con

Processor Uncore Configuration Registers332 Datasheet, Volume 24.2.5.3 TOLM—Top of Low Memory Register4.2.5.4 TOHM—Top of High Memory Register4.2.5.5

Datasheet, Volume 2 333Processor Uncore Configuration Registers45:26 RW-LB 00000hLimit address This field correspond to Addr[45:26] of the MMIO rule

Processor Uncore Configuration Registers334 Datasheet, Volume 24.2.5.6 MMCFG_Rule—MMCFG Rule for Interleave Decoder Register4.2.5.7 IOPORT_Target_LIST

Datasheet, Volume 2 335Processor Uncore Configuration Registers4.2.5.8 MMCFG_Target_LIST—MMCFG Target List Register4.2.5.9 MMIO_Target_LIST—MMIO Targ

Processor Uncore Configuration Registers336 Datasheet, Volume 24.2.5.10 IOAPIC_Target_LIST—IOAPIC Target List Register4.2.5.11 SAD_Target—SAD Target L

Datasheet, Volume 2 337Processor Uncore Configuration Registers4.2.5.12 SAD_Control—SAD Control Register4.2.6 Integrated Memory Controller Target Add

Processor Uncore Configuration Registers338 Datasheet, Volume 24.2.6.2 MCMTR—MC Memory Technology RegisterMCMTRBus: 1 Device: 15 Function: 0 Offset: 7

Datasheet, Volume 2 339Processor Uncore Configuration Registers4.2.6.3 TADWAYNESS_[0:11]—TAD Range Wayness, Limit and Target RegisterThere are total

Configuration Process and Registers34 Datasheet, Volume 2• Device 16: Integrated Memory Controller Channel 0, 1, 2 and 3. Device 16, Function 0, 1, 4

Processor Uncore Configuration Registers340 Datasheet, Volume 24.2.6.5 MC_INIT_STATE_G—Initialization State for Boot, Training and IOSAV RegisterThis

Datasheet, Volume 2 341Processor Uncore Configuration Registers4.2.6.6 RCOMP_TIMER—RCOMP Wait Timer RegisterDefines the time from IO starting to run

Processor Uncore Configuration Registers342 Datasheet, Volume 24.2.7 Integrated Memory Controller MemHot RegistersThese registers Control for the Inte

Datasheet, Volume 2 343Processor Uncore Configuration Registers4.2.7.2 MH_SENSE_500NS_CFG—MEMHOT Sense and 500 ns Config Register4.2.7.3 MH_DTYCYC_M

Processor Uncore Configuration Registers344 Datasheet, Volume 24.2.7.4 MH_IO_500NS_CNTR—MEMHOT Input Output and 500ns Counter RegisterMH_IO_500NS_CNT

Datasheet, Volume 2 345Processor Uncore Configuration Registers4.2.7.5 MH_CHN_ASTN—MEMHOT Domain Channel Association RegisterMH_CHN_ASTNBus: 1 Device

Processor Uncore Configuration Registers346 Datasheet, Volume 24.2.7.6 MH_TEMP_STAT—MEMHOT Temperature Status RegisterMH_TEMP_STATBus: 1 Device: 15 Fu

Datasheet, Volume 2 347Processor Uncore Configuration Registers4.2.7.7 MH_EXT_STAT RegisterCapture externally asserted MEM_HOT[1:0]# assertion detect

Processor Uncore Configuration Registers348 Datasheet, Volume 228 ROS-V 0hSMB_BUSY: SMBus Busy stateThis bit is set by iMC while an SMBus/I2C command

Datasheet, Volume 2 349Processor Uncore Configuration Registers4.2.8.2 SMBCMD_[0:1]—SMBus Command RegisterA write to this register initiates a DIMM E

Datasheet, Volume 2 35Configuration Process and Registers2.3 Configuration MechanismsThe processor is the originator of configuration cycles. Interna

Processor Uncore Configuration Registers350 Datasheet, Volume 24.2.8.3 SMBCntl_[0:1]—SMBus Control RegisterSMBCntl_[0:1]Bus: 1 Device: 15 Function: 0

Datasheet, Volume 2 351Processor Uncore Configuration Registers4.2.8.4 SMB_TSOD_POLL_RATE_CNTR_[0:1]—SMBus Clock Period Counter Register8RW-LB 0hSMB

Processor Uncore Configuration Registers352 Datasheet, Volume 24.2.8.5 SMB_STAT_1—SMBus Status RegisterThis register provides the interface to the SMB

Datasheet, Volume 2 353Processor Uncore Configuration Registers4.2.8.6 SMBCMD_1—SMBus Command RegisterA write to this register initiates a DIMM EEPRO

Processor Uncore Configuration Registers354 Datasheet, Volume 24.2.8.7 SMBCntl_1—SMBus Control Register15:0 RWS 0000hSMB_WDATA: Write DataHolds data t

Datasheet, Volume 2 355Processor Uncore Configuration Registers4.2.8.8 SMB_TSOD_POLL_RATE_CNTR_1—SMBus Clock Period Counter Register10 RW 0hSMB_SOFT

Processor Uncore Configuration Registers356 Datasheet, Volume 24.2.8.9 SMB_PERIOD_CFG—SMBus Clock Period Config Register4.2.8.10 SMB_PERIOD_CNTR—SMBus

Datasheet, Volume 2 357Processor Uncore Configuration Registers4.2.9 Integrated Memory Controller DIMM Memory Technology Type Registers 4.2.9.1 PXPCA

Processor Uncore Configuration Registers358 Datasheet, Volume 24.2.9.2 DIMMMTR_[0:2]—DIMM Memory Technology RegisterDIMMMTR_[0:2]Bus: 1 Device: 15 Fun

Datasheet, Volume 2 359Processor Uncore Configuration Registers4.2.10 Integrated Memory Controller Memory Target Address Decoder Registers4.2.10.1 TA

Configuration Process and Registers36 Datasheet, Volume 2§Caching Agent (CBo)3CE9h,3CEBh,3CEDh,3CEFh13 0–3 Unicast RegistersCaching Agent (CBo) 3CF4h

Processor Uncore Configuration Registers360 Datasheet, Volume 24.2.11 Integrated Memory Controller Channel Rank RegistersThere are a total of 6 RIR ra

Datasheet, Volume 2 361Processor Uncore Configuration Registers4.2.11.3 RIRILV1OFFSET_[0:4]—RIR Range Rank Interleave 1 OFFSET Register4.2.11.4 RIRI

Processor Uncore Configuration Registers362 Datasheet, Volume 24.2.11.5 RIRILV3OFFSET_[0:4]—RIR Range Rank Interleave 3 OFFSET Register4.2.11.6 RIRIL

Datasheet, Volume 2 363Processor Uncore Configuration Registers4.2.11.8 RIRILV6OFFSET_[0:4]—RIR Range Rank Interleave 6 OFFSET Register4.2.11.9 RIRI

Processor Uncore Configuration Registers364 Datasheet, Volume 24.2.11.10 RIRILV0OFFSET_1—RIR Range Rank Interleave 0 OFFSET Register4.2.11.11 RIRILV1

Datasheet, Volume 2 365Processor Uncore Configuration Registers4.2.11.12 RIRILV2OFFSET_1—RIR Range Rank Interleave 2 OFFSET Register4.2.11.13 RIRILV

Processor Uncore Configuration Registers366 Datasheet, Volume 24.2.11.14 RIRILV4OFFSET_1—RIR Range Rank Interleave 4 OFFSET Register4.2.11.15 RIRILV5

Datasheet, Volume 2 367Processor Uncore Configuration Registers4.2.11.16 RIRILV6OFFSET_1—RIR Range Rank Interleave 6 OFFSET Register4.2.11.17 RIRILV

Processor Uncore Configuration Registers368 Datasheet, Volume 24.2.11.18 RIRILV0OFFSET_2—RIR Range Rank Interleave 0 OFFSET Register4.2.11.19 RIRILV1

Datasheet, Volume 2 369Processor Uncore Configuration Registers4.2.11.20 RIRILV2OFFSET_2—RIR Range Rank Interleave 2 OFFSET Register4.2.11.21 RIRILV

Datasheet, Volume 2 37Processor Integrated I/O (IIO) Configuration Registers3 Processor Integrated I/O (IIO) Configuration Registers3.1 Processor IIO

Processor Uncore Configuration Registers370 Datasheet, Volume 24.2.11.22 RIRILV4OFFSET_2—RIR Range Rank Interleave 4 OFFSET Register4.2.11.23 RIRILV5

Datasheet, Volume 2 371Processor Uncore Configuration Registers4.2.11.24 RIRILV6OFFSET_2—RIR Range Rank Interleave 6 OFFSET Register4.2.11.25 RIRILV

Processor Uncore Configuration Registers372 Datasheet, Volume 24.2.11.26 RIRILV0OFFSET_3—RIR Range Rank Interleave 0 OFFSET Register4.2.11.27 RIRILV1

Datasheet, Volume 2 373Processor Uncore Configuration Registers4.2.11.28 RIRILV2OFFSET_3—RIR Range Rank Interleave 2 OFFSET Register4.2.11.29 RIRILV

Processor Uncore Configuration Registers374 Datasheet, Volume 24.2.11.30 RIRILV4OFFSET_3—RIR Range Rank Interleave 4 OFFSET Register4.2.11.31 RIRILV5

Datasheet, Volume 2 375Processor Uncore Configuration Registers4.2.11.32 RIRILV6OFFSET_3—RIR Range Rank Interleave 6 OFFSET Register4.2.11.33 RIRILV

Processor Uncore Configuration Registers376 Datasheet, Volume 24.2.11.34 RIRILV0OFFSET_4—RIR Range Rank Interleave 0 OFFSET Register4.2.11.35 RIRILV1

Datasheet, Volume 2 377Processor Uncore Configuration Registers4.2.11.36 RIRILV2OFFSET_4—RIR Range Rank Interleave 2 OFFSET Register4.2.11.37 RIRILV

Processor Uncore Configuration Registers378 Datasheet, Volume 24.2.11.38 RIRILV4OFFSET_4—RIR Range Rank Interleave 4 OFFSET Register4.2.11.39 RIRILV5

Datasheet, Volume 2 379Processor Uncore Configuration Registers4.2.11.40 RIRILV6OFFSET_4—RIR Range Rank Interleave 6 OFFSET Register4.2.11.41 RIRILV

Processor Integrated I/O (IIO) Configuration Registers38 Datasheet, Volume 2Note: VSEC stands for Vendor Specific Extended Capability. In DMI2 mode, A

Processor Uncore Configuration Registers380 Datasheet, Volume 24.2.12 Integrated Memory Controller Error Injection RegistersComplete address match (Ad

Datasheet, Volume 2 381Processor Uncore Configuration Registers4.2.12.3 RIRILV0OFFSET_[0:4]—RIR Range Rank Interleave 0 OFFSET Register4.2.12.4 RIRI

Processor Uncore Configuration Registers382 Datasheet, Volume 24.2.12.5 RIRILV2OFFSET_[0:4]—RIR Range Rank Interleave 2 OFFSET Register4.2.12.6 RIRIL

Datasheet, Volume 2 383Processor Uncore Configuration Registers4.2.12.7 RIRILV4OFFSET_[0:4]—RIR Range Rank Interleave 4 OFFSET Register4.2.12.8 RIRI

Processor Uncore Configuration Registers384 Datasheet, Volume 24.2.12.9 RIRILV6OFFSET_[0:4]—RIR Range Rank Interleave 6 OFFSET Register4.2.12.10 RIRI

Datasheet, Volume 2 385Processor Uncore Configuration Registers4.2.12.11 RIRILV0OFFSET_1—RIR Range Rank Interleave 0 OFFSET Register4.2.12.12 RIRILV

Processor Uncore Configuration Registers386 Datasheet, Volume 24.2.12.13 RIRILV2OFFSET_1—RIR Range Rank Interleave 2 OFFSET Register4.2.12.14 RIRILV3

Datasheet, Volume 2 387Processor Uncore Configuration Registers4.2.12.15 RIRILV4OFFSET_1—RIR Range Rank Interleave 4 OFFSET Register4.2.12.16 RIRILV

Processor Uncore Configuration Registers388 Datasheet, Volume 24.2.12.17 RIRILV6OFFSET_1—RIR Range Rank Interleave 6 OFFSET Register4.2.12.18 RIRILV7

Datasheet, Volume 2 389Processor Uncore Configuration Registers4.2.12.19 RIRILV0OFFSET_2—RIR Range Rank Interleave 0 OFFSET Register4.2.12.20 RIRILV

Datasheet, Volume 2 39Processor Integrated I/O (IIO) Configuration RegistersFigure 3-2 illustrates how each PCI Express/DMI2 port’s configuration spa

Processor Uncore Configuration Registers390 Datasheet, Volume 24.2.12.21 RIRILV2OFFSET_2—RIR Range Rank Interleave 2 OFFSET Register4.2.12.22 RIRILV3

Datasheet, Volume 2 391Processor Uncore Configuration Registers4.2.12.23 RIRILV4OFFSET_2—RIR Range Rank Interleave 4 OFFSET Register4.2.12.24 RIRILV

Processor Uncore Configuration Registers392 Datasheet, Volume 24.2.12.25 RIRILV6OFFSET_2—RIR Range Rank Interleave 6 OFFSET RegisterRIRILV6OFFSET_2Bu

Datasheet, Volume 2 393Processor Uncore Configuration Registers4.2.12.26 RIRILV7OFFSET_2—RIR Range Rank Interleave 7 OFFSET Register4.2.12.27 RIRILV

Processor Uncore Configuration Registers394 Datasheet, Volume 24.2.12.28 RIRILV1OFFSET_3—RIR Range Rank Interleave 1 OFFSET Register4.2.12.29 RIRILV2

Datasheet, Volume 2 395Processor Uncore Configuration Registers4.2.12.30 RIRILV3OFFSET_3—RIR Range Rank Interleave 3 OFFSET Register4.2.12.31 RIRILV

Processor Uncore Configuration Registers396 Datasheet, Volume 24.2.12.32 RIRILV5OFFSET_3—RIR Range Rank Interleave 5 OFFSET Register4.2.12.33 RIRILV6

Datasheet, Volume 2 397Processor Uncore Configuration Registers4.2.12.34 RIRILV7OFFSET_3—RIR Range Rank Interleave 7 OFFSET Register4.2.12.35 RIRILV

Processor Uncore Configuration Registers398 Datasheet, Volume 24.2.12.36 RIRILV1OFFSET_4—RIR Range Rank Interleave 1 OFFSET Register4.2.12.37 RIRILV2

Datasheet, Volume 2 399Processor Uncore Configuration Registers4.2.12.38 RIRILV3OFFSET_4—RIR Range Rank Interleave 3 OFFSET Register4.2.12.39 RIRILV

4 Datasheet, Volume 23.2.4.32 SNXTPTR—Subsystem ID Next Pointer Register...623.2.4.33 DMIRCBAR—DMI Root Complex Register Blo

Processor Integrated I/O (IIO) Configuration Registers40 Datasheet, Volume 23.2.3 IIO PCI Express* Configuration Space RegistersTable 3-1. (DMI2 Mode)

Processor Uncore Configuration Registers400 Datasheet, Volume 24.2.12.40 RIRILV5OFFSET_4—RIR Range Rank Interleave 5 OFFSET Register4.2.12.41 RIRILV6

Datasheet, Volume 2 401Processor Uncore Configuration Registers4.2.12.42 RIRILV7OFFSET_4—RIR Range Rank Interleave 7 OFFSET Register4.2.12.43 RSP_FU

Processor Uncore Configuration Registers402 Datasheet, Volume 24.2.12.44 RSP_FUNC_ADDR_MATCH_HI RegisterComplete address match (Addr[45:3]) and mask i

Datasheet, Volume 2 403Processor Uncore Configuration Registers4.2.12.46 RSP_FUNC_ADDR_MASK_HI RegisterComplete address match (Addr[45:3]) and mask i

Processor Uncore Configuration Registers404 Datasheet, Volume 24.2.13.2 ET_CFG—Electrical Throttling Configuration RegisterET_CFGBus: 1 Device: 16 Fun

Datasheet, Volume 2 405Processor Uncore Configuration Registers4.2.13.3 CHN_TEMP_CFG—Channel TEMP Configuration Register4.2.13.4 CHN_TEMP_STAT—Channe

Processor Uncore Configuration Registers406 Datasheet, Volume 24.2.13.5 DIMM_TEMP_OEM_[0:2]—DIMM TEMP Configuration RegisterDIMM_TEMP_OEM_[0:2]Bus: 1

Datasheet, Volume 2 407Processor Uncore Configuration Registers4.2.13.6 DIMM_TEMP_TH_[0:2]—DIMM TEMP Configuration RegisterDIMM_TEMP_TH_[0:2]Bus: 1 D

Processor Uncore Configuration Registers408 Datasheet, Volume 24.2.13.7 DIMM_TEMP_THRT_LMT_[0:2]—DIMM TEMP Configuration RegisterAll three THRT_CRIT,

Datasheet, Volume 2 409Processor Uncore Configuration Registers4.2.13.8 DIMM_TEMP_EV_OFST_[0:2]—DIMM TEMP Configuration RegisterDIMM_TEMP_EV_OFST_[0

Datasheet, Volume 2 41Processor Integrated I/O (IIO) Configuration RegistersTable 3-2. (DMI2) Extended Configuration Map – Device 0/Function 0 – Off

Processor Uncore Configuration Registers410 Datasheet, Volume 24.2.13.9 DIMMTEMPSTAT_[0:2]—DIMM TEMP Status RegisterDIMMTEMPSTAT_[0:2]Bus: 1 Device: 1

Datasheet, Volume 2 411Processor Uncore Configuration Registers4.2.13.10 PM_CMD_PWR_[0:2]—Electrical Power and Thermal Throttling Command Power Regi

Processor Uncore Configuration Registers412 Datasheet, Volume 24.2.13.11 ET_DIMM_AVG_SUM_[0:2]—Electrical Throttling Energy Accumulator Register4.2.1

Datasheet, Volume 2 413Processor Uncore Configuration Registers4.2.13.13 THRT_PWR_DIMM_[0:2]—THRT_PWR_DIMM_0 Registerbit[10:0]: Max number of transac

Processor Uncore Configuration Registers414 Datasheet, Volume 226:25 RW 00bPower Down Clock Modes for UDIMM The field defines how CK and CK# are turne

Datasheet, Volume 2 415Processor Uncore Configuration Registers4.2.13.15 MC_TERM_RNK_MSK—MC Termination Rank Mask Register4.2.13.16 PM_SREF—PM Self-R

Processor Uncore Configuration Registers416 Datasheet, Volume 24.2.13.17 PM_DLL—PM DLL Config RegisterThis register controls the master and slave DLL

Datasheet, Volume 2 417Processor Uncore Configuration Registers4.2.13.18 ET_CH_AVG—Electrical Throttling Energy Averager Register4.2.13.19 ET_CH_SUM—

Processor Uncore Configuration Registers418 Datasheet, Volume 24.2.14 Integrated Memory Controller DIMM Channels Timing Registers4.2.14.1 TCDBP—Timin

Datasheet, Volume 2 419Processor Uncore Configuration Registers4.2.14.2 TCRAP—Timing Constraints DDR3 Regular Access Parameter RegisterTCRAPBus: 1 D

Processor Integrated I/O (IIO) Configuration Registers42 Datasheet, Volume 2Table 3-3. (DMI2) Mode Extended Configuration Map – Device 0/Function 0 –

Processor Uncore Configuration Registers420 Datasheet, Volume 24.2.14.3 TCRWP—Timing Constraints DDR3 Read Write Parameter RegisterTCRWPBus: 1 Device

Datasheet, Volume 2 421Processor Uncore Configuration Registers2:0 RW 2hT_RRDR Back to back READ to READ from different RANK separation parameter. T

Processor Uncore Configuration Registers422 Datasheet, Volume 24.2.14.4 TCOTHP—Timing Constraints DDR3 Other Timing Parameter RegisterTCOTHPBus: 1 De

Datasheet, Volume 2 423Processor Uncore Configuration Registers4.2.14.5 TCRFP—Timing Constraints DDR3 Refresh Parameter Register4.2.14.6 TCRFTP—Timin

Processor Uncore Configuration Registers424 Datasheet, Volume 24.2.14.7 TCSRFTP—Timing Constraints Self-Refresh Timing Parameter Register4.2.14.8 TCM

Datasheet, Volume 2 425Processor Uncore Configuration Registers4.2.14.9 TCZQCAL—Timing Constraints ZQ Calibration Timing Parameter Register14:12 RW

Processor Uncore Configuration Registers426 Datasheet, Volume 24.2.14.10 TCSTAGGER_REF RegisterThis register provides the tRFC like timing constraint

Datasheet, Volume 2 427Processor Uncore Configuration Registers4.2.14.12 RPQAGE RegisterThis register allows the Read of Pending Queue Age Counters.

Processor Uncore Configuration Registers428 Datasheet, Volume 24.2.14.14 RDIMMTIMINGCNTL—RDIMM Timing Parameter Register27:21 RW 06hOPC_TH: Overdue Pa

Datasheet, Volume 2 429Processor Uncore Configuration Registers4.2.14.15 RDIMMTIMINGCNTL2 Register4.2.14.16 TCMRS—DDR3 MRS Timing Register4.2.14.17 R

Datasheet, Volume 2 43Processor Integrated I/O (IIO) Configuration RegistersTable 3-4. Device 1/Functions 0-1 (PCIe* Root Ports), Devices 2/Functions

Processor Uncore Configuration Registers430 Datasheet, Volume 24.2.14.18 RD_ODT_TBL1—Read ODT Lookup Table 1 RegisterOne entry for each physical rank

Datasheet, Volume 2 431Processor Uncore Configuration Registers4.2.14.19 RD_ODT_TBL2—Read ODT Lookup Table 2 RegisterOne entry for each physical rank

Processor Uncore Configuration Registers432 Datasheet, Volume 24.2.14.20 WR_ODT_TBL0—Write ODT Lookup Table 0 RegisterOne entry for each physical rank

Datasheet, Volume 2 433Processor Uncore Configuration Registers4.2.14.21 WR_ODT_TBL1—Write ODT Lookup Table 1 RegisterOne entry for each physical ran

Processor Uncore Configuration Registers434 Datasheet, Volume 24.2.14.22 WR_ODT_TBL2—Write ODT Lookup Table 2 RegisterOne entry for each physical rank

Datasheet, Volume 2 435Processor Uncore Configuration Registers4.2.14.24 RSP_FUNC_MCCTRL_ERR_INJ RegisterError Injection Response FunctionThis regist

Processor Uncore Configuration Registers436 Datasheet, Volume 24.2.14.26 WDBWM—WDB Watermarks RegisterThis register configures the WMM behavior – wate

Datasheet, Volume 2 437Processor Uncore Configuration Registers4.2.14.28 SPARING RegisterThis is the Sparing Credit register 4.2.15 Integrated Memory

Processor Uncore Configuration Registers438 Datasheet, Volume 24.2.15.2 IOSAV_CH_ADDR_UPDT_[0:3]—IOSAV Channel Address Update Seq 0 RegisterNeed to a

Datasheet, Volume 2 439Processor Uncore Configuration Registers4.2.15.3 IOSAV_CH_ADDR_LFSR_[0:3]— IOSAV Channel Address LFSR Seq 0 RegisterThe RW-L

Processor Integrated I/O (IIO) Configuration Registers44 Datasheet, Volume 2Table 3-5. Device 1/Functions 0–1 (PCIe* Root Ports), Devices 2/Functions

Processor Uncore Configuration Registers440 Datasheet, Volume 24.2.15.5 IOSAV_CH_SUBSEQ_CTRL_[0:3]—IOSAV Channel Sub-Sequence Control Seq 0 RegisterT

Datasheet, Volume 2 441Processor Uncore Configuration Registers4.2.15.6 IOSAV_CH_SEQ_CTRL—IOSAV Channel Sequence Control RegisterThe RW-L field is l

Processor Uncore Configuration Registers442 Datasheet, Volume 24.2.15.7 IOSAV_CH_STAT—IOSAV Channel Status RegisterThis register is cleared when writi

Datasheet, Volume 2 443Processor Uncore Configuration Registers4.2.15.8 IOSAV_CH_DATA_CNTL—IOSAV Channel Data Control RegisterThis register controls

Processor Uncore Configuration Registers444 Datasheet, Volume 24.2.16 Integrated Memory Controller Error Registers4.2.16.1 ROUNDTRIP0—Round-Trip Laten

Datasheet, Volume 2 445Processor Uncore Configuration Registers4.2.16.3 IOLATENCY0—IO Latency Register4.2.16.4 IOLATENCY1—IO Latency 1 RegisterIOLATE

Processor Uncore Configuration Registers446 Datasheet, Volume 24.2.16.5 WDBPRELOADREG0—WDB Data Load Register 04.2.16.6 WDBPRELOADREG1—WDB Data Load R

Datasheet, Volume 2 447Processor Uncore Configuration Registers4.2.16.7 WDBPRELOADCTRL—WDB Preload Control RegisterThe following is an example to pro

Processor Uncore Configuration Registers448 Datasheet, Volume 24.2.16.8 CORRERRCNT_0—Corrected Error Count RegisterThis register has per Rank correcte

Datasheet, Volume 2 449Processor Uncore Configuration Registers4.2.16.9 CORRERRCNT_1—Corrected Error Count RegisterThis register has per Rank correct

Datasheet, Volume 2 45Processor Integrated I/O (IIO) Configuration RegistersNote:1. Applicable to Device 0,2,3/Function 0.2. Applicable to Device 2/F

Processor Uncore Configuration Registers450 Datasheet, Volume 24.2.16.11 CORRERRCNT_3—Corrected Error Count RegisterThis register has per Rank correct

Datasheet, Volume 2 451Processor Uncore Configuration Registers4.2.16.13 CORRERRTHRSHLD_1—Corrected Error Threshold RegisterThis register holds the p

Processor Uncore Configuration Registers452 Datasheet, Volume 24.2.16.16 CORRERRORSTATUS—Corrected Error Status RegisterThis register holds per rank c

Datasheet, Volume 2 453Processor Uncore Configuration Registers4.2.16.17 LEAKY_BKT_2ND_CNTR_REG RegisterLEAKY_BKT_2ND_CNTR_REGBus: 1 Device: 16 Funct

Processor Uncore Configuration Registers454 Datasheet, Volume 24.2.16.18 DEVTAG_CNTRL[0:7]—Device Tagging Control for Logical Rank 0 RegisterUsage mo

Datasheet, Volume 2 455Processor Uncore Configuration Registers4.2.16.19 IOSAV_CH_B0_B3_BW_SERR RegisterWhen an error occurs on one of the data pins,

Processor Uncore Configuration Registers456 Datasheet, Volume 24.2.16.21 IOSAV_CH_B8_BW_SERR RegisterWhen an error occurs on one of the data pins, the

Datasheet, Volume 2 457Processor Uncore Configuration Registers4.2.16.23 IOSAV_CH_B4_B7_BW_MASK RegisterIOSAV bit-wise compare mask registers – Each

Processor Uncore Configuration Registers458 Datasheet, Volume 24.2.16.25 IOSAV_DQ_LFSR[0:2] Register4.2.16.26 IOSAV_DQ_LFSRSEED[0:2] RegisterIOSAV_DQ_

Datasheet, Volume 2 459Processor Uncore Configuration Registers4.2.16.27 IOSAV_DQ_LFSR1 Register4.2.16.28 IOSAV_DQ_LFSRSEED1 RegisterIOSAV_DQ_LFSR1Bu

Processor Integrated I/O (IIO) Configuration Registers46 Datasheet, Volume 2Table 3-7. Device 0/Function 0 DMI2 mode), Devices 2/Functions 0 (PCIe* Ro

Processor Uncore Configuration Registers460 Datasheet, Volume 24.2.16.29 IOSAV_DQ_LFSR2 Register4.2.16.30 IOSAV_DQ_LFSRSEED2 RegisterIOSAV_DQ_LFSR2Bus

Datasheet, Volume 2 461Processor Uncore Configuration Registers4.2.16.31 MCSCRAMBLECONFIG—Data Scrambler Configuration RegisterThis register is used

Processor Uncore Configuration Registers462 Datasheet, Volume 24.2.16.33 RSP_FUNC_CRC_ERR_INJ_DEV0_XOR_MSK RegisterError Injection Response Function o

Datasheet, Volume 2 463Processor Uncore Configuration Registers4.2.16.35 RSP_FUNC_CRC_ERR_INJ_EXTRA RegisterThis register is provides the Error Injec

Processor Uncore Configuration Registers464 Datasheet, Volume 24.2.16.36 x4modesel—MDCP X4 Mode Select Registerx4modeselBus: 1 Device: 16 Function: 2

Datasheet, Volume 2 465Processor Uncore Configuration Registers4.3 Processor Home Agent Registers 4.3.1 CSR Register MapsThe following register maps

Processor Uncore Configuration Registers466 Datasheet, Volume 24.3.2 Processor Home Agent RegisterThe Home agent is responsible for memory transaction

Datasheet, Volume 2 467Processor Uncore Configuration Registers4.3.2.3 HaCrdtCnt—Home Agent Credit Counter RegisterThese registers are used for HA cr

Processor Uncore Configuration Registers468 Datasheet, Volume 216 RW 0bShared Credit Release When set, prevents schedulers from speculatively allocati

Datasheet, Volume 2 469Processor Uncore Configuration Registers12:8 RW 0hType of Credit to Be Accessed The HA has two schedulers. Each scheduler uses

Datasheet, Volume 2 47Processor Integrated I/O (IIO) Configuration Registers3.2.4 Standard PCI Configuration Space (Type 0/1 Common Configuration Sp

Processor Uncore Configuration Registers470 Datasheet, Volume 24.3.2.4 HtBase—Home Track Base Selection RegisterEach node has 4 bits mapping to the as

Datasheet, Volume 2 471Processor Uncore Configuration Registers4.3.2.5 HABGFTune—HA BGF Tuning RegisterThe flow accommodates BGF sync pulse frequenci

Processor Uncore Configuration Registers472 Datasheet, Volume 24.4 Power Control Unit (PCU) Registers4.4.1 CSR Register MapsThe following register map

Datasheet, Volume 2 473Processor Uncore Configuration RegistersTable 4-21. PCU1 Register Map: Device: 10 Function: 1 DID VID 0h 80hPCISTS PCICMD 4h8

Processor Uncore Configuration Registers474 Datasheet, Volume 2Table 4-22. PCU2 Register Map Table: Device: 10 Function: 2 DID VID 0hPRIMARY_PLANE_RA

Datasheet, Volume 2 475Processor Uncore Configuration RegistersTable 4-23. PCU2 Register Map Table: Device: 10 Function: 3 DID VID 0h CAP_HDR 80hPCI

Processor Uncore Configuration Registers476 Datasheet, Volume 24.4.2 PCU0 Registers4.4.2.1 MEM_TRML_ESTIMATION_CONFIG—Memory Thermal Estimation Confi

Datasheet, Volume 2 477Processor Uncore Configuration Registers4.4.2.2 MEM_TRML_ESTIMATION_CONFIG2—Memory Thermal Estimation Configuration 2 Registe

Processor Uncore Configuration Registers478 Datasheet, Volume 24.4.2.4 MEM_ACCUMULATED_BW_CH_[0:3]—MEM_ACCUMULATED_BW_CH_0 RegisterThis register cont

Datasheet, Volume 2 479Processor Uncore Configuration Registers4.4.2.7 PACKAGE_POWER_SKU_UNIT—Package Power SKU Unit RegisterThis register defines un

Processor Integrated I/O (IIO) Configuration Registers48 Datasheet, Volume 23.2.4.3 PCICMD—PCI Command RegisterPCICMDBus: 0 Device: 0 Function: 0 Offs

Processor Uncore Configuration Registers480 Datasheet, Volume 24.4.2.9 PLATFORM_ID—Platform ID RegisterUsed for selecting which patch to use. 4.4.2.10

Datasheet, Volume 2 481Processor Uncore Configuration Registers4.4.2.11 PP0_Any_Thread_Activity—PP0_Any_Thread_Activity RegisterThis register will co

Processor Uncore Configuration Registers482 Datasheet, Volume 24.4.2.14 Package_Temperature RegisterPackage temperature in degrees (C).4.4.2.15 PP0_te

Datasheet, Volume 2 483Processor Uncore Configuration Registers4.4.2.17 P_STATE_LIMITS—P-State Limits RegisterThis register allows software to limit

Processor Uncore Configuration Registers484 Datasheet, Volume 24.4.2.18 TEMPERATURE_TARGET—Temperature Target RegisterThis Legacy register holds tempe

Datasheet, Volume 2 485Processor Uncore Configuration Registers46:32 RW-L 0000hPackage Power Limit 2 This field indicates the power limitation #2. Th

Processor Uncore Configuration Registers486 Datasheet, Volume 24.4.2.20 PRIP_TURBO_PWR_LIM—Primary Plane Turbo Power Limitation RegisterThis register

Datasheet, Volume 2 487Processor Uncore Configuration Registers4.4.2.21 PRIMARY_PLANE_CURRENT_CONFIG_CONTROL—Primary Plane Current Configuration Con

Processor Uncore Configuration Registers488 Datasheet, Volume 24.4.3 PCU1 Registers4.4.3.1 SSKPD—Sticky Scratchpad Data RegisterThis register holds 64

Datasheet, Volume 2 489Processor Uncore Configuration Registers4.4.3.3 PCIE_ILTR_OVRD—PCI Express* Latency Tolerance Requirement (LTR) Override Regi

Datasheet, Volume 2 49Processor Integrated I/O (IIO) Configuration Registers3.2.4.4 PCISTS—PCI Status Register1RW0bMemory Space Enable 1 = Enables a

Processor Uncore Configuration Registers490 Datasheet, Volume 24.4.3.4 BIOS_MAILBOX_DATA—BIOS Mailbox Data RegisterThis is the Data register for the B

Datasheet, Volume 2 491Processor Uncore Configuration Registers4.4.3.6 BIOS_RESET_CPL—BIOS Reset Complete RegisterThis register is used as interface

Processor Uncore Configuration Registers492 Datasheet, Volume 24RW1S0bMemory Calibration Done Used to Facilitate handshake between BIOS and PcodeMemor

Datasheet, Volume 2 493Processor Uncore Configuration Registers4.4.3.7 MC_BIOS_REQ—MC_BIOS_REQ RegisterThis register allows BIOS to request Memory Co

Processor Uncore Configuration Registers494 Datasheet, Volume 24.4.3.9 SAPMCTL—System Agent Power Management Control RegisterPCODE will sample this re

Datasheet, Volume 2 495Processor Uncore Configuration Registers12 RW-L 1bNon-Snoop Wakeup Triggers Self Refresh Exit When this bit is set to 1b, a No

Processor Uncore Configuration Registers496 Datasheet, Volume 24.4.3.10 M_COMP—Memory COMP Control Register4.4.3.11 SAPMTIMERS—System Agent Power Mana

Datasheet, Volume 2 497Processor Uncore Configuration Registers4.4.3.12 RINGTIMERS—RING Timers RegisterRING Timers in 10n s granularity. 4.4.3.13 BAN

Processor Uncore Configuration Registers498 Datasheet, Volume 24.4.4 PCU2 Registers4.4.4.1 CPU_BUS_NUMBER—CPU Bus Number RegisterThis register is used

Datasheet, Volume 2 499Processor Uncore Configuration Registers4.4.4.4 GLOBAL_PKG_C_S_CONTROL RegisterThis register is in the PCU CR space. It contai

Datasheet, Volume 2 53.2.4.89 PCIE_IOU_BIF_CTRL—PCIe* Port Bifurcation Control Register... 1083.2.4.90 PXP2CAP—Secondary PCI Express* Extended Cap

Processor Integrated I/O (IIO) Configuration Registers50 Datasheet, Volume 212 RW1C 0bReceived Target AbortThis bit is set when a device experiences a

Processor Uncore Configuration Registers500 Datasheet, Volume 24.4.4.5 GLOBAL_NID_MAP_REGISTER_0 RegisterThis reister is in the PCU CR space. It conta

Datasheet, Volume 2 501Processor Uncore Configuration Registers4.4.4.6 PKG_CST_ENTRY_CRITERIA_MASK RegisterThis register is used to configure which e

Processor Uncore Configuration Registers502 Datasheet, Volume 24.4.4.8 PACKAGE_RAPL_PERF_STATUS RegisterThis register is used by Pcode to report Packa

Datasheet, Volume 2 503Processor Uncore Configuration Registers4.4.4.10 DRAM_ENERGY_STATUS RegisterDRAM energy consumed by all the DIMMS in all the C

Processor Uncore Configuration Registers504 Datasheet, Volume 24.4.4.12 DRAM_PLANE_POWER_LIMIT—DRAM Plane Power Limit RegisterThis register is used by

Datasheet, Volume 2 505Processor Uncore Configuration Registers4.4.4.14 PERF_P_LIMIT_CONTROL RegisterThis register is BIOS configurable. Dual mapping

Processor Uncore Configuration Registers506 Datasheet, Volume 24.4.4.15 IO_BANDWIDTH_P_LIMIT_CONTROL RegisterThis register provides various controls.

Datasheet, Volume 2 507Processor Uncore Configuration Registers4.4.4.16 MCA_ERR_SRC_LOG—MCA Error Source Log RegisterMCSourceLog is used by the PCU t

Processor Uncore Configuration Registers508 Datasheet, Volume 24.4.4.18 THERMTRIP_CONFIG—ThermTrip Configuration RegisterThis register is used to conf

Datasheet, Volume 2 509Processor Uncore Configuration Registers4.4.5 PCU3 Registers4.4.5.1 DEVHIDE[0:7]—Function 0 Device Hide RegisterThis register

Datasheet, Volume 2 51Processor Integrated I/O (IIO) Configuration Registers3.2.4.5 RID—Revision Identification Register3.2.4.6 CCR—Class Code Regist

Processor Uncore Configuration Registers510 Datasheet, Volume 24.4.5.3 CAPID0 RegisterThis register is a processor Capability Register used to expose

Datasheet, Volume 2 511Processor Uncore Configuration Registers4.4.5.4 CAPID1 RegisterThis register is a processor Capability Register used to expose

Processor Uncore Configuration Registers512 Datasheet, Volume 229:26 RO-FW 0000bDMFC This field controls which values may be written to the Memory Fr

Datasheet, Volume 2 513Processor Uncore Configuration Registers4.4.5.5 CAPID2 RegisterThis register is a processor Capability Register used to expose

Processor Uncore Configuration Registers514 Datasheet, Volume 24.4.5.6 CAPID3 RegisterThis register is a processor Capability Register used to expose

Datasheet, Volume 2 515Processor Uncore Configuration Registers4.4.5.7 CAPID4 RegisterThis register is a Capability Register used to expose enable/di

Processor Uncore Configuration Registers516 Datasheet, Volume 24.4.5.8 FLEX_RATIO—Flexible Ratio RegisterThis ’flexible boot’ register is written by B

Datasheet, Volume 2 517Processor Uncore Configuration Registers4.5 Processor Utility Box (UBOX) RegistersThe Utility Box is the piece of the processo

Processor Uncore Configuration Registers518 Datasheet, Volume 2Table 4-25. Scratchpad and Semaphore Registers (Device 11, Function 3) DID VID 0h BIOS

Datasheet, Volume 2 519Processor Uncore Configuration Registers4.5.2 Processor Utility Box (UBOX) Registers4.5.2.1 CPUNODEID—Node ID Configuration Re

Processor Integrated I/O (IIO) Configuration Registers52 Datasheet, Volume 23.2.4.8 PLAT—Primary Latency Timer Register3.2.4.9 HDR—Header Type Registe

Processor Uncore Configuration Registers520 Datasheet, Volume 24.5.2.3 IntControl—Interrupt Control RegisterInterrupt Configuration Register IntContro

Datasheet, Volume 2 521Processor Uncore Configuration Registers4.5.2.4 LockControl—Lock Control Register4.5.2.5 GIDNIDMAP—Node ID Mapping RegisterMap

Processor Uncore Configuration Registers522 Datasheet, Volume 24.5.2.6 CoreCount—Number of Cores RegisterReflection of the LTCount2 register 4.5.2.7 U

Datasheet, Volume 2 523Processor Uncore Configuration Registers4.5.2.8 EVENTS_DEBUG RegisterEvent bus control 4.5.3 ScratchPad and Semaphore Register

Processor Uncore Configuration Registers524 Datasheet, Volume 24.5.3.3 LocalSemaphore[0:1]—Local Semaphore 0 RegisterunCore Semaphore register is a re

Datasheet, Volume 2 525Processor Uncore Configuration Registers4.5.3.4 SystemSemaphore[0:1]—System Semaphore 0 RegisterunCore Semaphore register is a

Processor Uncore Configuration Registers526 Datasheet, Volume 24.5.3.5 DEVHIDE[0:7]—Device Hide 0 RegisterDevice Hide Register in CSR space 4.5.3.6 CP

Datasheet, Volume 2 527Processor Uncore Configuration Registers4.5.3.8 ABORTDEBUG1—Abort Debug RegisterAbort debug for aborting accesses 4.5.3.9 ABOR

Processor Uncore Configuration Registers528 Datasheet, Volume 24.6 Performance Monitoring (PMON) Registers4.6.1 CSR Register MapsThe following registe

Datasheet, Volume 2 529Processor Uncore Configuration Registers4.6.2 Processor Performance Monitor Registers4.6.2.1 PmonCtr[0:4]—PMON Counter 4.6.2.2

Datasheet, Volume 2 53Processor Integrated I/O (IIO) Configuration Registers3.2.4.11 BIST—Built-In Self Test Register3.2.4.12 PBUS—Primary Bus Number

Processor Uncore Configuration Registers530 Datasheet, Volume 24.6.2.4 PmonCntrCfg_[0:4]—Performance Counter Control RegisterPmonCntrCfgBus: 1 Device:

Datasheet, Volume 2 531Processor Uncore Configuration Registers4.6.2.5 PmonUnitCtrl—Performance Unit Control Register16 WO 0hQueue Occupancy Reset T

Processor Uncore Configuration Registers532 Datasheet, Volume 24.6.2.6 PmonUnitStatus—Performance Unit Status RegisterThis field shows which registers

Datasheet, Volume 2 533Processor Uncore Configuration Registers4.6.2.7 HaPerfmonAddrMatch0—Home Agent Perfmon Address Match Register 0These register

Processor Uncore Configuration Registers534 Datasheet, Volume 24.6.2.10 HAPmonDbgCtrl—HA Perfmon Debug Control RegisterControl register for the specia

Datasheet, Volume 2 535Processor Uncore Configuration Registers4.7 R2PCIe Routing Table and Ring Credits4.7.1 R2PCIe Routing Register MapTable 4-27.

Processor Uncore Configuration Registers536 Datasheet, Volume 24.7.1.1 IIO_BW_COUNTER—IIO Bandwidth Counter Register4.7.1.2 R2PGNCTRL—R2PCIe General C

Datasheet, Volume 2 537Processor Uncore Configuration Registers4.7.1.4 R2PINGERRMSK0 Register4.7.1.5 R2PINGDBG RegisterR2PINGERRMSK0Bus: 1 Device: 19

Processor Uncore Configuration Registers538 Datasheet, Volume 24.7.1.6 R2PEGRDBG Register4.7.1.7 R2PDEBUG—R2PCIe Debug RegisterR2PEGRDBGBus: 1 Device:

Datasheet, Volume 2 539Processor Uncore Configuration Registers4.7.1.8 R2EGRERRLOG RegisterR2EGRERRLOGBus: 1 Device: 19 Function: 0 Offset: B0hBit At

Processor Integrated I/O (IIO) Configuration Registers54 Datasheet, Volume 23.2.4.15 IOBAS—I/O Base Register3.2.4.16 IOLIM—I/O Limit RegisterIOBASBus:

Processor Uncore Configuration Registers540 Datasheet, Volume 24.7.1.9 R2EGRERRMSK RegisterR2EGRERRMSKBus: 1 Device: 19 Function: 0 Offset: B8hBit Att

Datasheet, Volume 2 541Processor Uncore Configuration Registers4.7.1.10 R2PCIE_DBG_BUS_CONTROL Register4.7.1.11 R2PCIE_DBG_BUS_MATCH Register4.7.1.12

Processor Uncore Configuration Registers542 Datasheet, Volume 24.7.1.14 R2PCIE_ASC_LDVAL Register4.7.1.15 R2PCIE_ASC_CONTROL Register4.7.1.16 R2PCIE_G

Datasheet, Volume 2 543Processor Uncore Configuration Registers4.8 MISC Registers4.8.1 DDRIOTrainingModeA[0:1]—DDRIOTrainingMode RegisterDDRIOTrainin

Processor Uncore Configuration Registers544 Datasheet, Volume 24.8.2 DDRIOTrainingResult1A[0:1]—DDRIOTrainingResult1 Register4.8.3 DDRIOTrainingResul

Datasheet, Volume 2 545Processor Uncore Configuration Registers4.8.4 DDRIOBuffCfgA[0:1]—DDRIOBuffCfg RegisterDDRIOBuffCfgA[0:1]Bus: 1 Device: 17 Func

Processor Uncore Configuration Registers546 Datasheet, Volume 24.8.5 DDRIOTXRXBotRank0A[0:1]—DDRIOTXRXBotRank0 RegisterDDRIOTXRXBotRank0A[0:1]Bus: 1

Datasheet, Volume 2 547Processor Uncore Configuration Registers4.8.6 DDRIORXTopRank0A[0:1]—DDRIORXTopRank0 Register4.8.7 DDRIOTXTopRank0A[0:1]—DDRIOT

Processor Uncore Configuration Registers548 Datasheet, Volume 24.8.8 DDRIOCtlPICode0A[0:1]—DDRIOCtlPICode0 RegisterDDRIOCtlPICode0A[0:1]Bus: 1 Device:

Datasheet, Volume 2 549Processor Uncore Configuration Registers4.8.9 DDRIOCtlPICode1A[0:1]—DDRIOCtlPICode1 RegisterDDRIOCtlPICode1A[0:1]Bus: 1 Device

Datasheet, Volume 2 55Processor Integrated I/O (IIO) Configuration Registers3.2.4.17 SECSTS—Secondary Status RegisterSECSTSBus: 0 Device: 0 Function:

Processor Uncore Configuration Registers550 Datasheet, Volume 24.8.10 DDRIOLogicDelayA[0:1]—DDRIOLogicDelay RegisterLogic delay control register. When

Datasheet, Volume 2 551Processor Uncore Configuration Registers4.8.12 DDRIOCmdPICodeA[0:1]—DDRIOCmdPICode RegisterDDRIOCmdPICodeA[0:1]Bus: 1 Device:

Processor Uncore Configuration Registers552 Datasheet, Volume 24.8.13 DDRIOCkRankUsedA[0:1]—DDRIOCkRankUsed RegisterDDRIOCkRankUsedA[0:1]Bus: 1 Device

Datasheet, Volume 2 553Processor Uncore Configuration Registers4.8.14 DDRIOCkPiCode0A[0:1]—DDRIOCkPiCode0 RegisterDefines PI coding for DDR CK pins:C

Processor Uncore Configuration Registers554 Datasheet, Volume 24.8.15 DDRIOCkPiCode1A[0:1]—DDRIOCkPiCode1 RegisterDefines PI coding for DDR CK pins:Ch

Datasheet, Volume 2 555Processor Uncore Configuration Registers4.8.16 DDRIOCkLogicDelayA[0:1]—DDRIOCkLogicDelay RegisterLogic delay of 1 QCLK in CLK

Processor Uncore Configuration Registers556 Datasheet, Volume 24.8.18 DDRIOCompOVR5A[0:1] RegisterTCO evaluation5:3 RW-LB 100bOFSTMirror_CR_drvcmdl1

Datasheet, Volume 2 557Processor Uncore Configuration Registers4.8.19 DDRIOCompCfgSPDA[0:1] RegisterNote: Only channel 1 or channel 3 are connected t

Processor Uncore Configuration Registers558 Datasheet, Volume 24.8.20 QPIREUT_PM_R0—REUT Power Management Register 0QPIREUT_PM_R0Bus: 1 Device: 8 Func

Datasheet, Volume 2 559Processor Uncore Configuration Registers21:16 RWS-LV 0hTL0sWakeRemote: TL0S_WAKE_REMOTELink Select must always be used to disp

Processor Integrated I/O (IIO) Configuration Registers56 Datasheet, Volume 23.2.4.18 MBAS—Memory Base Register3.2.4.19 MLIM—Memory Limit RegisterMBASB

Processor Uncore Configuration Registers560 Datasheet, Volume 24.8.21 TXALIGN_EN Register5:0 RWS-L 12hTL0sWake: TL0S_WAKEIf # of links supported is gr

Datasheet, Volume 2 561Processor Uncore Configuration Registers4.8.22 TXEQ_LVL0_0 Register4.8.23 TXEQ_LVL0_1 Register4.8.24 TXEQ_LVL1_0 RegisterTXEQ_

Processor Uncore Configuration Registers562 Datasheet, Volume 24.8.25 TXEQ_LVL1_1 Register4.8.26 TXEQ_LVL2_0 Register4.8.27 TXEQ_LVL2_1 RegisterTXEQ_L

Datasheet, Volume 2 563Processor Uncore Configuration Registers4.8.28 TXEQ_LVL3_0 Register4.8.29 FWDC_LCPKAMP_CFG Register§ §TXEQ_LVL3_0Bus: 1 Device

Processor Uncore Configuration Registers564 Datasheet, Volume 2

Datasheet, Volume 2 57Processor Integrated I/O (IIO) Configuration Registers3.2.4.20 PBAS—Prefetchable Memory Base Register3.2.4.21 PLIM—Prefetchable

Processor Integrated I/O (IIO) Configuration Registers58 Datasheet, Volume 23.2.4.23 PLIMU—Prefetchable Memory Limit (Upper 32 bits) Register3.2.4.24

Datasheet, Volume 2 59Processor Integrated I/O (IIO) Configuration Registers3.2.4.25 SDID—Subsystem Identity3.2.4.26 CAPPTR—Capability Pointer3.2.4.2

6 Datasheet, Volume 23.2.8.14 DMIESD—DMI Element self Description Register...1423.2.8.15 DMILED—DMI Link Entry Description Regi

Processor Integrated I/O (IIO) Configuration Registers60 Datasheet, Volume 23.2.4.29 INTPIN—Interrupt Pin Register3.2.4.30 BCTRL—Bridge Control Regist

Datasheet, Volume 2 61Processor Integrated I/O (IIO) Configuration Registers3.2.4.31 SCAPID—Subsystem Capability Identity Register5RO 0bMaster Abort

Processor Integrated I/O (IIO) Configuration Registers62 Datasheet, Volume 23.2.4.32 SNXTPTR—Subsystem ID Next Pointer Register3.2.4.33 DMIRCBAR—DMI R

Datasheet, Volume 2 63Processor Integrated I/O (IIO) Configuration Registers3.2.4.35 MSINXTPTR—MSI Next Pointer Register3.2.4.36 MSIMSGCTL—MSI Contro

Processor Integrated I/O (IIO) Configuration Registers64 Datasheet, Volume 23.2.4.37 MSIMSGCTL—MSI Control RegisterMSIMSGCTLBus: 0 Device: 3 Function:

Datasheet, Volume 2 65Processor Integrated I/O (IIO) Configuration Registers3.2.4.38 MSGADR—MSI Address RegisterThe MSI Address Register (MSIAR) cont

Processor Integrated I/O (IIO) Configuration Registers66 Datasheet, Volume 23.2.4.41 MSIPENDING—MSI Pending Bit Register3.2.4.42 PXPCAPID—PCI Express*

Datasheet, Volume 2 67Processor Integrated I/O (IIO) Configuration Registers3.2.4.44 PXPCAP—PCI Express* Capabilities RegisterPXPCAPBus: 0 Device: 0

Processor Integrated I/O (IIO) Configuration Registers68 Datasheet, Volume 23.2.4.45 DEVCAP—PCI Express* Device Capabilities RegisterDEVCAPBus: 0 Devi

Datasheet, Volume 2 69Processor Integrated I/O (IIO) Configuration Registers3.2.4.46 DEVCTRL—PCI Express* Device Control RegisterDEVCTRLBus: 0 Device

Datasheet, Volume 2 73.3.3.26 VTGENCTRL—Intel® VT-d General Control Register... 1733.3.3.27 VTISOCHCTRL—Intel® VT-d Isoch Related C

Processor Integrated I/O (IIO) Configuration Registers70 Datasheet, Volume 21RW0bNon Fatal Error Reporting EnableThis bit controls the reporting of no

Datasheet, Volume 2 71Processor Integrated I/O (IIO) Configuration Registers3.2.4.47 DEVSTS—PCI Express* Device Status RegisterDEVSTSBus: 0 Device: 0

Processor Integrated I/O (IIO) Configuration Registers72 Datasheet, Volume 23.2.4.48 LNKCAP—PCI Express* Link Capabilities RegisterThe Link Capabiliti

Datasheet, Volume 2 73Processor Integrated I/O (IIO) Configuration Registers3.2.4.49 LNKCON—PCI Express* Link Control RegisterThe PCI Express Link Co

Processor Integrated I/O (IIO) Configuration Registers74 Datasheet, Volume 28RO0bEnable Clock Power Management Not Applicable to processor7RW0bExtend

Datasheet, Volume 2 75Processor Integrated I/O (IIO) Configuration Registers3.2.4.50 LNKSTS—PCI Express* Link Status RegisterThe PCI Express Link Sta

Processor Integrated I/O (IIO) Configuration Registers76 Datasheet, Volume 23.2.4.51 SLTCAP—PCI Express* Slot Capabilities RegisterThe Slot Capabiliti

Datasheet, Volume 2 77Processor Integrated I/O (IIO) Configuration Registers6RW-O 0bHot-plug Capable This field defines hot-plug support capabilitie

Processor Integrated I/O (IIO) Configuration Registers78 Datasheet, Volume 23.2.4.52 SLTCON—PCI Express* Slot Control RegisterAny write to this regist

Datasheet, Volume 2 79Processor Integrated I/O (IIO) Configuration Registers9:8 RW 3hPower Indicator Control If a Power Indicator is implemented, wr

8 Datasheet, Volume 23.3.5.12 IRPP1ERRCTL—IRP Protocol Error Control Register...2083.3.5.13 IRPP1FFERRST—IRP Protocol Fatal FERR S

Processor Integrated I/O (IIO) Configuration Registers80 Datasheet, Volume 23.2.4.53 SLTSTS—PCI Express* Slot Status RegisterThe PCI Express Slot Stat

Datasheet, Volume 2 81Processor Integrated I/O (IIO) Configuration Registers3.2.4.54 ROOTCON—PCI Express* Root Control Register5RO 0bMRL Sensor State

Processor Integrated I/O (IIO) Configuration Registers82 Datasheet, Volume 22RW0bSystem Error on Fatal Error Enable This field enables notifying the

Datasheet, Volume 2 83Processor Integrated I/O (IIO) Configuration Registers3.2.4.55 ROOTCAP—PCI Express* Root Capabilities Register0RW0bSystem Error

Processor Integrated I/O (IIO) Configuration Registers84 Datasheet, Volume 23.2.4.56 ROOTSTS—PCI Express* Root Status Register3.2.4.57 DEVCAP2—PCI Exp

Datasheet, Volume 2 85Processor Integrated I/O (IIO) Configuration Registers3.2.4.58 DEVCTRL2—PCI Express* Device Control Register 29RW-O 0bAtomicOp

Processor Integrated I/O (IIO) Configuration Registers86 Datasheet, Volume 23.2.4.59 LNKCAP2—PCI Express* Link Capabilities 2 Register4RW1bCompletion

Datasheet, Volume 2 87Processor Integrated I/O (IIO) Configuration Registers3.2.4.60 LNKCON2—PCI Express* Link Control 2 Register LNKCON2Bus: 0 Devic

Processor Integrated I/O (IIO) Configuration Registers88 Datasheet, Volume 23.2.4.61 LNKSTS2—PCI Express* Link Status Register 2LNKSTS2Bus: 0 Device:

Datasheet, Volume 2 89Processor Integrated I/O (IIO) Configuration Registers3.2.4.62 PMCAP—Power Management Capabilities RegisterThe PM Capabilities

Datasheet, Volume 2 93.3.7.5 APICID Register... 2293.3.7.6 VER—Version Register...

Processor Integrated I/O (IIO) Configuration Registers90 Datasheet, Volume 23.2.4.63 PMCSR—Power Management Control and Status RegisterThis register p

Datasheet, Volume 2 91Processor Integrated I/O (IIO) Configuration Registers3.2.4.64 XPREUT_HDR_EXT—REUT PCIe* Header Extended Register3.2.4.65 XPREU

Processor Integrated I/O (IIO) Configuration Registers92 Datasheet, Volume 23.2.4.66 XPREUT_HDR_LEF—REUT Header Leaf Capability Register3.2.4.67 ACSCA

Datasheet, Volume 2 93Processor Integrated I/O (IIO) Configuration Registers3.2.4.68 ACSCAP—Access Control Services Capability Register ACSCAPBus: 0

Processor Integrated I/O (IIO) Configuration Registers94 Datasheet, Volume 23.2.4.69 ACSCTRL—Access Control Services Control Register3.2.4.70 APICBASE

Datasheet, Volume 2 95Processor Integrated I/O (IIO) Configuration Registers3.2.4.71 APICLIMIT—APIC Limit Register3.2.4.72 VSECHDR—PCI Express* Enhan

Processor Integrated I/O (IIO) Configuration Registers96 Datasheet, Volume 23.2.4.74 ERRCAPHDR—PCI Express* Enhanced Capability Header Register – Roo

Datasheet, Volume 2 97Processor Integrated I/O (IIO) Configuration Registers3.2.4.76 UNCERRMSK—Uncorrectable Error Mask RegisterThis register masks u

Processor Integrated I/O (IIO) Configuration Registers98 Datasheet, Volume 23.2.4.78 CORERRSTS—Correctable Error Status RegisterThis register identifi

Datasheet, Volume 2 99Processor Integrated I/O (IIO) Configuration Registers3.2.4.80 ERRCAP—Advanced Error Capabilities and Control Register3.2.4.81