Intel CM8063701391600 Scheda Tecnica

Document Number: 322909-006 Intel® Core™ i5-600, i3-500 Desktop Processor Series, Intel® Pentium® Desktop Processor 6000 SeriesDatasheet – Volume 1Thi

Introduction10 Datasheet, Volume 1Figure 1-1. Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series P

100 Datasheet, Volume 1Processor Land and Signal InformationVSS F23 GNDVSS F26 GNDVSS F29 GNDVSS F32 GNDVSS F35 GNDVSS F38 GNDVSS F8 GNDVSS G13 GNDVSS

Datasheet, Volume 1 101Processor Land and Signal InformationVSS R4 GNDVSS T33 GNDVSS T36 GNDVSS T37 GNDVSS T38 GNDVSS T39 GNDVSS T5 GNDVSS U4 GNDVSS V

102 Datasheet, Volume 1Processor Land and Signal Information§ §VTT V8 PWRVTT W1 PWRVTT W6 PWRVTT Y33 PWRVTT Y34 PWRVTT Y35 PWRVTT Y36 PWRVTT Y37 PWRVT

Datasheet, Volume 1 11Introduction1.1 Processor Feature Details•Two cores• A 32-KB instruction and 32-KB data first-level cache (L1) for each core• A

Introduction12 Datasheet, Volume 1• 1-Gb and 2-Gb DDR3 DRAM technologies are supported.• Using 2-Gb device technologies, the largest memory capacity p

Datasheet, Volume 1 13Introduction• 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always

Introduction14 Datasheet, Volume 11.2.4 Platform Environment Control Interface (PECI)The PECI is a one-wire interface that provides a communication ch

Datasheet, Volume 1 15Introduction1.3 Power Management Support1.3.1 Processor Core• Full support of ACPI C-states as implemented by the following proc

Introduction16 Datasheet, Volume 1DMA Direct Memory AccessDMI Direct Media InterfaceDTS Digital Thermal SensorECC Error Correction CodeEnhanced Intel

Datasheet, Volume 1 17IntroductionProcessor CoreThe term “processor core” refers to Si die itself which can contain multiple execution cores. Each exe

Introduction18 Datasheet, Volume 11.7 Related DocumentsRefer to the following documents for additional information. § §Table 1-1. Related DocumentsDoc

Datasheet, Volume 1 19Interfaces2 InterfacesThis chapter describes the interfaces supported by the processor. 2.1 System Memory Interface2.1.1 System

2 Datasheet, Volume 1INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER

Interfaces20 Datasheet, Volume 1Note: DIMM module support is based on availability and is subject to change.2.1.2 System Memory Timing SupportThe IMC

Datasheet, Volume 1 21Interfaces2.1.3 System Memory Organization ModesThe IMC supports two memory organization modes, single-channel and dual-channel.

Interfaces22 Datasheet, Volume 1When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the

Datasheet, Volume 1 23Interfaces2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)The following sections describe the Just-in-Tim

Interfaces24 Datasheet, Volume 12.2 PCI Express* InterfaceThis section describes the PCI Express interface capabilities of the processor. See the PCI

Datasheet, Volume 1 25InterfacesPCI Express uses packets to communicate information between components. Packets are formed in the Transaction and Data

Interfaces26 Datasheet, Volume 12.2.2 PCI Express* Configuration MechanismThe PCI Express (external graphics) link is mapped through a PCI-to-PCI brid

Datasheet, Volume 1 27Interfaces2.3 Direct Media Interface (DMI)DMI connects the processor and the PCH chip-to-chip. The DMI is similar to a four-lane

Interfaces28 Datasheet, Volume 12.4.1 3D and Video Engines for Graphics ProcessingThe 3D graphics pipeline architecture simultaneously operates on dif

Datasheet, Volume 1 29Interfaces2.4.1.2.3 Geometry Shader (GS) StageThe GS stage receives inputs from the VS stage. Compiled application-provided GS p

Datasheet, Volume 1 3Contents1Introduction...

Interfaces30 Datasheet, Volume 12.4.1.4.2 Logical 128-Bit Fixed BLT and 256 Fill EngineThis BLT engine accelerates the GUI of Microsoft Windows* opera

Datasheet, Volume 1 31Interfaces2.4.2 Integrated Graphics Display The Graphics Processing Unit’s display pipe can be broken down into three components

Interfaces32 Datasheet, Volume 12.4.2.1.3 Cursors A and BCursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration, and ar

Datasheet, Volume 1 33Interfaces2.5 Platform Environment Control Interface (PECI)The PECI is a one-wire interface that provides a communication channe

Interfaces34 Datasheet, Volume 1

Datasheet, Volume 1 35Technologies3 Technologies3.1 Intel® Virtualization TechnologyIntel Virtualization Technology (Intel VT) makes a single system a

Technologies36 Datasheet, Volume 1• Guest Preemption Timer— Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specifi

Datasheet, Volume 1 37Technologies3.1.5 Intel® VT-d Features Not SupportedThe following features are not supported by the processor with Intel VT-d:•

Technologies38 Datasheet, Volume 13.3 Intel® Hyper-Threading TechnologyThe processor supports Intel® Hyper-Threading Technology (Intel® HT Technology)

Datasheet, Volume 1 39Power Management4 Power ManagementThis chapter provides information on the following power management topics:•ACPI States• Proce

4 Datasheet, Volume 12.4.2.1 Display Planes ...312.4.2.2 Display Pipes...

Power Management40 Datasheet, Volume 14.1.4 PCI Express* Link States4.1.5 Integrated Graphics States4.1.6 Interface State CombinationsState Descriptio

Datasheet, Volume 1 41Power Management4.2 Processor Core Power ManagementWhile executing code, Enhanced Intel SpeedStep Technology optimizes the proce

Power Management42 Datasheet, Volume 1Entry and exit of the C-States at the thread and core level are shown in Figure 4-2.While individual threads can

Datasheet, Volume 1 43Power ManagementNote:1. If enabled, the core C-state will be C1E if all active cores have also resolved to a core C1 state or hi

Power Management44 Datasheet, Volume 14.2.4 Core C-statesThe following are general rules for all core C-states, unless specified otherwise:• A core C-

Datasheet, Volume 1 45Power Management4.2.4.5 C-State Auto-DemotionIn general, deeper C-states, such as C6, have long latencies and have higher energy

Power Management46 Datasheet, Volume 1Table 4-6 shows an example package C-state resolution for a dual-core processor. Figure 4-3 summarizes package C

Datasheet, Volume 1 47Power Management4.2.5.2 Package C1/C1ENo additional power reduction actions are taken in the package C1 state. However, if the C

Power Management48 Datasheet, Volume 14.3 Integrated Memory Controller (IMC) Power ManagementThe main memory is power managed during normal operation

Datasheet, Volume 1 49Power Management4.3.2.3 Dynamic Power Down OperationDynamic power-down of memory is employed during normal operation. Based on i

Datasheet, Volume 1 56 Signal Description ...536.1 Sys

Power Management50 Datasheet, Volume 14.5 Integrated Graphics Power Management4.5.1 Graphics Render C-StateRender C-State (RC6) is a technique designe

Datasheet, Volume 1 51Thermal Management5 Thermal ManagementFor thermal specifications and design guidelines, refer to the appropriate Thermal and Mec

Thermal Management52 Datasheet, Volume 1

Datasheet, Volume 1 53Signal Description6 Signal DescriptionThis chapter describes the processor signals. They are arranged in functional groups accor

Signal Description54 Datasheet, Volume 16.1 System Memory InterfaceTable 6-2. Memory Channel ASignal Name Description Direction TypeSA_BS[2:0]Bank Se

Datasheet, Volume 1 55Signal DescriptionTable 6-3. Memory Channel BSignal Name Description Direction TypeSB_BS[2:0]Bank Select: These signals define

Signal Description56 Datasheet, Volume 16.2 Memory Reference and Compensation6.3 Reset and Miscellaneous SignalsTable 6-4. Memory Reference and Compen

Datasheet, Volume 1 57Signal DescriptionCOMP2Impedance compensation must be terminated on the system board using a precision resistor. Refer to Table

Signal Description58 Datasheet, Volume 16.4 PCI Express* Based Interface Signals6.5 DMI—Processor to PCH Serial Interface6.6 PLL SignalsTable 6-6. PCI

Datasheet, Volume 1 59Signal Description6.7 Intel® Flexible Display Interface Signals6.8 JTAG/ITP SignalsTable 6-9. Intel® Flexible Display Interface

6 Datasheet, Volume 18-2 Socket Pinmap (Top View, Upper-Right Quadrant) ...868-3 Socket Pinmap (T

Signal Description60 Datasheet, Volume 16.9 Error and Thermal ProtectionTable 6-11. Error and Thermal ProtectionSignal Name Description Direction Typ

Datasheet, Volume 1 61Signal Description6.10 Power Sequencing6.11 Processor Core Power SignalsTable 6-12. Power SequencingSignal Name Description Dir

Signal Description62 Datasheet, Volume 1VID[7:6]VID[5:3]/CSC[2:0]VID[2:0]/MSID[2:0]VID[7:0] (Voltage ID) are used to support automatic selection of po

Datasheet, Volume 1 63Signal Description6.12 Graphics and Memory Core Power Signals6.13 Ground and NCTFTable 6-14. Graphics and Memory Power SignalsSi

Signal Description64 Datasheet, Volume 16.14 Processor Internal Pull Up/Pull Down§ §Table 6-16. Processor Internal Pull Up/Pull DownSignal NamePull Up

Datasheet, Volume 1 65Electrical Specifications7 Electrical Specifications7.1 Power and Ground Lands The processor has VCC, VTT, VDDQ, VCCPLL, VAXG, a

Electrical Specifications66 Datasheet, Volume 17.3 Processor Clocking (BCLK[0], BCLK#[0])The processor uses a differential clock to generate the proce

Datasheet, Volume 1 67Electrical Specifications7.5 Graphics Voltage Identification (GFX_VID)A dedicated voltage regulator is required to deliver volta

Electrical Specifications68 Datasheet, Volume 10 0 0 1 0 1 1 0 1.47500 0 1 1 1 0 0 0 1 0.906250 0 0 1 0 1 1 1 1.46875 0 1 1 1 0 0 1 0 0.900000 0 0 1 1

Datasheet, Volume 1 69Electrical Specifications0 0 1 1 1 1 1 0 1.22500 1 0 0 1 1 0 0 1 0.656250 0 1 1 1 1 1 1 1.21875 1 0 0 1 1 0 1 0 0.650000 1 0 0 0

Datasheet, Volume 1 7Revision History§ §Revision NumberDescription Date001 • Initial releaseJanuary 2010002 • Added workstation informationJanuary 201

Electrical Specifications70 Datasheet, Volume 1Notes:1. The MSID[2:0] signals are provided to indicate the maximum platform capability to the processo

Datasheet, Volume 1 71Electrical SpecificationsTable 7-3. Signal Groups (Sheet 1 of 2)1Signal GroupAlpha GroupType SignalsSystem Reference ClockDiffer

Electrical Specifications72 Datasheet, Volume 1Notes:1. Refer to Chapter 6 for signal description details.2. SA and SB refer to DDR3 Channel A and DDR

Datasheet, Volume 1 73Electrical Specifications7.8 Test Access Port (TAP) ConnectionDue to the voltage levels supported by other components in the Tes

Electrical Specifications74 Datasheet, Volume 17.10 DC SpecificationsThe processor DC specifications in this section are defined at the processor pads

Datasheet, Volume 1 75Electrical SpecificationsNotes:1. VTT must be provided using a separate voltage source and not be connected to VCC. The voltage

Electrical Specifications76 Datasheet, Volume 1Notes:1. VAXG is VID based rail.Notes:1. The VCC_MIN and VCC_MAX loadlines represent static and transie

Datasheet, Volume 1 77Electrical Specifications3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Volta

Electrical Specifications78 Datasheet, Volume 1Notes:1. The VAXG_MIN and VAXG_MAX loadlines represent static and transient limits. 2. This table is in

Datasheet, Volume 1 79Electrical SpecificationsNotes:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2.

8 Datasheet, Volume 1

Electrical Specifications80 Datasheet, Volume 1Notes:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2.

Datasheet, Volume 1 81Electrical SpecificationsNotes:1. Refer to the PCI Express Base Specification for more details.2. VTX-AC-CM-PP and VTX-AC-CM-P a

Electrical Specifications82 Datasheet, Volume 17.11 Platform Environmental Control Interface (PECI) DC SpecificationsPECI is an Intel proprietary inte

Datasheet, Volume 1 83Electrical Specifications7.11.2 Input Device HysteresisThe input buffers in both client and host models must use a Schmitt-trigg

Electrical Specifications84 Datasheet, Volume 1

Datasheet, Volume 1 85Processor Land and Signal Information8 Processor Land and Signal Information8.1 Processor Land AssignmentsThe processor land-map

Processor Land and Signal Information86 Datasheet, Volume 1Figure 8-2. Socket Pinmap (Top View, Upper-Right Quadrant) 2019181716151413121110987654321S

Datasheet, Volume 1 87Processor Land and Signal InformationFigure 8-3. Socket Pinmap (Top View, Lower-Left Quadrant) YVTT VTT VTT VTT VTT VTTWVSS VSS

Processor Land and Signal Information88 Datasheet, Volume 1Figure 8-4. Socket Pinmap (Top View, Lower-Right Quadrant)BCLK#[1]VSSFDI_TX[7]FDI_TX#[7]FDI

Datasheet, Volume 1 89Processor Land and Signal InformationTable 8-1. Processor Pin List by Pin NamePin Name Pin # Buffer Type Dir.BCLK_ITP AK39 CMOS

Datasheet, Volume 1 9Introduction1 Introduction The Intel® Core™ i5-600, i3-500 desktop processor series and Intel® Pentium® desktop processor 6000 se

90 Datasheet, Volume 1Processor Land and Signal InformationGFX_VID[6] J11 CMOS OGFX_VR_EN F12 CMOS OISENSE T40 Analog IPECI AG35 Asynch I/OPEG_CLK AA3

Datasheet, Volume 1 91Processor Land and Signal InformationRSVD AK12RSVD AK13RSVD AK14RSVD AK15RSVD AK16RSVD AK18RSVD AK25RSVD AK26RSVD AK27RSVD AK28R

92 Datasheet, Volume 1Processor Land and Signal InformationSA_DQ[16] AT4 DDR3 I/OSA_DQ[17] AU2 DDR3 I/OSA_DQ[18] AW3 DDR3 I/OSA_DQ[19] AW4 DDR3 I/OSA_

Datasheet, Volume 1 93Processor Land and Signal InformationSA_MA[14] AT11 DDR3 OSA_MA[15] AR10 DDR3 OSA_MA[2] AV15 DDR3 OSA_MA[3] AU15 DDR3 OSA_MA[4]

94 Datasheet, Volume 1Processor Land and Signal InformationSB_DQ[45] AR31 DDR3 I/OSB_DQ[46] AR34 DDR3 I/OSB_DQ[47] AT33 DDR3 I/OSB_DQ[48] AR35 DDR3 I/

Datasheet, Volume 1 95Processor Land and Signal InformationVAXG A15 PWRVAXG A17 PWRVAXG A18 PWRVAXG B14 PWRVAXG B15 PWRVAXG B17 PWRVAXG B18 PWRVAXG C1

96 Datasheet, Volume 1Processor Land and Signal InformationVCC D36 PWRVCC D38 PWRVCC D39 PWRVCC E22 PWRVCC E23 PWRVCC E25 PWRVCC E26 PWRVCC E28 PWRVCC

Datasheet, Volume 1 97Processor Land and Signal InformationVCC K36 PWRVCC K38 PWRVCC K39 PWRVCC L17 PWRVCC L19 PWRVCC L20 PWRVCC L22 PWRVCC L23 PWRVCC

98 Datasheet, Volume 1Processor Land and Signal InformationVID[6] U34 CMOS I/OVID[7] U33 CMOS I/OVSS A16 GNDVSS A25 GNDVSS A28 GNDVSS A34 GNDVSS A37 G

Datasheet, Volume 1 99Processor Land and Signal InformationVSS AP26 GNDVSS AP27 GNDVSS AP29 GNDVSS AP33 GNDVSS AP35 GNDVSS AP38 GNDVSS AP4 GNDVSS AP7