Intel EU80574XL088N Scheda Tecnica

Document Number:319128-001Intel® Core™2 Extreme Processor QX9775ΔDatasheetFebruary 2008

Introduction10 DatasheetThe processor is intended for high performance server and workstation systems. The processor supports a Dual Independent Bus (

Datasheet 11Introductiontwo processor agents. The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth.• Func

Introduction12 Datasheet1.2 ReferencesMaterial and concepts available in the following documents may be beneficial when reading this document.§§Docume

Datasheet 13Electrical Specifications2 Electrical Specifications2.1 Front Side Bus and GTLREFMost processor FSB signals use Assisted Gunning Transceiv

Electrical Specifications14 Datasheet2.3 Decoupling GuidelinesDue to its large number of transistors and high internal clock speeds, the processor is

Datasheet 15Electrical Specifications2.4 Front Side Bus Clock (BCLK[1:0]) and Processor ClockingBCLK[1:0] directly controls the FSB interface speed as

Electrical Specifications16 Datasheet2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])Upon power up, the FSB frequency is set to the maximum s

Datasheet 17Electrical Specifications2.5 Voltage Identification (VID)The Voltage Identification (VID) specification for the processor is defined by th

Electrical Specifications18 DatasheetNOTES:1. When the “111111” VID pattern is observed, the voltage regulator output should be disabled.2. The VID ra

Datasheet 19Electrical SpecificationsNOTE: The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.NOTE: The MS_ID[1:0]

2 Datasheet INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO

Electrical Specifications20 Datasheet2.7 Front Side Bus Signal GroupsThe FSB signals have been combined into groups by buffer type. AGTL+ input signal

Datasheet 21Electrical SpecificationsNOTES:1. Refer to Section 4.2 for signal descriptions.2. These signals may be driven simultaneously by multiple a

Electrical Specifications22 Datasheet2.8 CMOS Asynchronous and Open Drain Asynchronous SignalsLegacy input signals such as A20M#, IGNNE#, INIT#, SMI#,

Datasheet 23Electrical SpecificationsNOTE:1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications.2. The leakage

Electrical Specifications24 Datasheet2.11 Mixing ProcessorsIntel supports and validates dual processor configurations only in which both processors op

Datasheet 25Electrical SpecificationsNOTES:1. For functional operation, all processor electrical, signal quality, mechanical and thermal specification

Electrical Specifications26 DatasheetNOTES:1. Unless otherwise noted, all specifications in this table are based on final silicon characterization dat

Datasheet 27Electrical Specifications8. Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) shown in Figure 5-

Electrical Specifications28 DatasheetNOTES:1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. See Section 2.13.1 for VCC over

Datasheet 29Electrical SpecificationsNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. VIL is de

Datasheet 3Contents1 Introduction...91.1

Electrical Specifications30 DatasheetNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. The VTT r

Datasheet 31Electrical SpecificationsNOTES:1. VOS is the measured overshoot voltage.2. TOS is the measured time duration above VID.2.13.2 Die Voltage

Electrical Specifications32 Datasheet2.14 AGTL+ FSB SpecificationsRouting topologies are dependent on the processors supported and the chipset used in

Datasheet 33Electrical SpecificationsNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. Crossing

Electrical Specifications34 Datasheet§ §Figure 2-5. Differential Clock WaveformFigure 2-6. Differential Clock Crosspoint SpecificationFigure 2-7. D

Datasheet 35Mechanical Specifications3 Mechanical SpecificationsThe processor is packaged in a Flip Chip Land Grid Array (FC-LGA) package that interfa

Mechanical Specifications36 DatasheetNOTE: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the coo

Datasheet 37Mechanical SpecificationsFigure 3-3. Processor Package Drawing (Sheet 2 of 3)

Mechanical Specifications38 DatasheetFigure 3-4. Processor Package Drawing (Sheet 3 of 3)

Datasheet 39Mechanical Specifications3.2 Processor Component Keepout ZonesThe processor may contain components on the substrate that define component

4 Datasheet Figures2-1 Input Device Hysteresis...232-2 Proce

Mechanical Specifications40 Datasheet3.4 Package Handling GuidelinesTable 3-2 includes a list of guidelines on a package handling in terms of recommen

Datasheet 41Mechanical Specifications3.8 Processor MarkingsFigure 3-5 shows the topside markings on the processor. This diagram aids in the identifica

Mechanical Specifications42 Datasheet3.9 Processor Land CoordinatesFigure 3-6 and Figure 3-7 show the top and bottom view of the processor land coordi

Datasheet 43Mechanical Specifications§Figure 3-7. Processor Land Coordinates, Bottom ViewVTT/ Clocks1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2

Mechanical Specifications44 Datasheet

Datasheet 45Land Listing and Signal Description4 Land Listing and Signal Description4.1 Land ListingTable 4-1 is a listing of all processor lands orde

Land Listing and Signal Description46 DatasheetTable 4-1. Land Listing by Land Name (Sheet 1 of 17)Land NameLand No.Signal Buffer TypeDirectionA3# M5

Land Listing and Signal DescriptionDatasheet 47D27# G13 Source Sync Input/OutputD28# F14 Source Sync Input/OutputD29# G14 Source Sync Input/OutputD30#

Land Listing and Signal Description48 DatasheetRESERVED AE4RESERVED AE6RESERVED AH2RESERVED AH7RESERVED AJ3RESERVED AJ7RESERVED AK3RESERVED AM2RESERVE

Land Listing and Signal DescriptionDatasheet 49VCC AE9 Power/OtherVCC AF11 Power/OtherVCC AF12 Power/OtherVCC AF14 Power/OtherVCC AF15 Power/OtherVCC

Datasheet 5Revision HistoryRevision Description Date-001 Initial release February 2008

Land Listing and Signal Description50 DatasheetVCC AM8 Power/OtherVCC AM9 Power/OtherVCC AN11 Power/OtherVCC AN12 Power/OtherVCC AN14 Power/OtherVCC A

Land Listing and Signal DescriptionDatasheet 51VCC W8 Power/OtherVCC Y23 Power/OtherVCC Y24 Power/OtherVCC Y25 Power/OtherVCC Y26 Power/OtherVCC Y27 P

Land Listing and Signal Description52 DatasheetVSS AG7 Power/OtherVSS AH1 Power/OtherVSS AH10 Power/OtherVSS AH13 Power/OtherVSS AH16 Power/OtherVSS A

Land Listing and Signal DescriptionDatasheet 53VSS D9 Power/OtherVSS E11 Power/OtherVSS E14 Power/OtherVSS E17 Power/OtherVSS E2 Power/OtherVSS E20 Po

Land Listing and Signal Description54 DatasheetVSS V27 Power/Other VSS V28 Power/Other VSS V29 Power/Other VSS V3 Power/Other VSS V30 Power/Other

Land Listing and Signal DescriptionDatasheet 55Table 4-2. Land Listing by Land Number (Sheet 1 of 17)Pin No.Pin NameSignal Buffer TypeDirectionA2 VSS

Land Listing and Signal Description56 DatasheetD8 D12# Source Sync Input/OutputD9 VSS Power/OtherD10 D22# Source Sync Input/OutputD11 D15# Source Sync

Land Listing and Signal DescriptionDatasheet 57G9 D16# Source Sync Input/OutputG10GTLREF_ADD_ENDPower/Other InputG11 DBI1# Source Sync Input/OutputG12

Land Listing and Signal Description58 DatasheetK23 VCC Power/OtherK24 VCC Power/OtherK25 VCC Power/OtherK26 VCC Power/OtherK27 VCC Power/OtherK28 VCC

Land Listing and Signal DescriptionDatasheet 59T5 A09# Source Sync Input/OutputT6 VSS Power/OtherT7 VSS Power/OtherT8 VCC Power/OtherT23 VCC Power/Oth

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Land Listing and Signal Description60 DatasheetAB1 VSS Power/OtherAB2 IERR# Open Drain OutputAB3 MCERR# Common Clk Input/OutputAB4 A26# Source Sync In

Land Listing and Signal DescriptionDatasheet 61AF15 VCC Power/OtherAF16 VSS Power/OtherAF17 VSS Power/OtherAF18 VCC Power/OtherAF19 VCC Power/OtherAF2

Land Listing and Signal Description62 DatasheetAJ17 VSS Power/OtherAJ18 VCC Power/OtherAJ19 VCC Power/OtherAJ20 VSS Power/OtherAJ21 VCC Power/OtherAJ2

Land Listing and Signal DescriptionDatasheet 63AM18 VCC Power/OtherAM19 VCC Power/OtherAM20 VSS Power/OtherAM21 VCC Power/OtherAM22 VCC Power/OtherAM2

Land Listing and Signal Description64 Datasheet4.2 Signal DefinitionsTable 4-1. Signal Definitions (Sheet 1 of 11)Name Type Description NotesA[37:3]#

Datasheet 65Land Listing and Signal DescriptionAP[1:0]# I/OAP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[37:3]#, an

Land Listing and Signal Description66 DatasheetBPM5#BPM4# BPM3#BPM[2:1]#BPM0#I/OOI/OOI/OBPM[5:0]# (Breakpoint Monitor) are breakpoint and performance

Datasheet 67Land Listing and Signal DescriptionD[63:0]# I/OD[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the

Land Listing and Signal Description68 DatasheetDBSY# I/ODBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor F

Datasheet 69Land Listing and Signal DescriptionFERR#/PBE# OFERR#/PBE# (floating-point error/pending break event) is a multiplexed signal and its meani

Datasheet 7Intel® Core™2 Extreme Processor QX9775Δ FeaturesThe Intel Core™2 Extreme processor QX9775, designed for dual-socket configurations, deliver

Land Listing and Signal Description70 DatasheetIGNNE# IIGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and

Datasheet 71Land Listing and Signal DescriptionMCERR# I/OMCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus pro

Land Listing and Signal Description72 DatasheetRESET# IAsserting the RESET# signal resets all processors to known states and invalidates their interna

Datasheet 73Land Listing and Signal DescriptionTCK ITCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Acces

Land Listing and Signal Description74 DatasheetNOTES:1. For this processor land, the maximum number of symmetric agents is one. Maximum number of prio

Datasheet 75Thermal Specifications5 Thermal Specifications5.1 Package Thermal SpecificationsThe processor requires a thermal solution to maintain temp

Thermal Specifications76 Datasheetdetails on this feature, refer to Section 5.2. Thermal Monitor 1 and Thermal Monitor 2 feature must be enabled for

Datasheet 77Thermal Specifications5.1.2 Thermal MetrologyThe minimum and maximum case temperatures (TCASE) are specified in Table 5-2 is measured at t

Thermal Specifications78 DatasheetNOTE: Figure is not to scale and is for reference only.5.2 Processor Thermal Features5.2.1 Intel® Thermal Monitor Fe

Datasheet 79Thermal SpecificationsWhen the TM1 is enabled, and a high temperature situation exists (that is, TCC is active), the clocks will be modula

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Thermal Specifications80 Datasheetvoltage transition back to the normal system operating point. Transition of the VID code will occur first, in order

Datasheet 81Thermal SpecificationsPROCHOT# is designed to assert at or a few degrees higher than maximum TCASE when dissipating TDP power, and cannot

Thermal Specifications82 DatasheetFigure 5-4. Processor PECI TopologyPECI Host ControllerDomain00x30Domain10x30Domain00x31Domain10x31Processor(Socket

Datasheet 83Thermal Specifications5.3.1.1 TCONTROL and TCC Activation on PECI-based SystemsFan speed control solutions based on PECI utilize a TCONTRO

Thermal Specifications84 Datasheet5.3.2 PECI Specifications5.3.2.1 PECI Device AddressThe PECI device address for socket 0 is 30h and socket 1 is 31h.

Datasheet 85Features6 Features6.1 Power-On Configuration OptionsSeveral configuration options can be configured by hardware. The processor samples its

Features86 Datasheet6.2.1 Normal StateThis is the normal operating state for the processor.6.2.2 HALT or Extended HALT StateThe Extended HALT state (C

Datasheet 87FeaturesThe system can generate a STPCLK# while the processor is in the HALT state. When the system deasserts STPCLK#, the processor will

Features88 DatasheetRESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition ba

Datasheet 89Features6.3 Enhanced Intel SpeedStep® TechnologyThe processor supports Enhanced Intel SpeedStep® Technology. This technology enables the p

Datasheet 9Introduction1 IntroductionThe Intel® Core™2 Extreme processor QX9775 is a server/workstation processor using four 45-nm Hi-k next generatio

Features90 Datasheet