Intel HH80553PG0964MN Scheda Tecnica

Document Number: 310306-007Intel® Pentium® D Processor 900Δ Sequence and Intel® Pentium® Processor Extreme Edition 955Δ, 965ΔDatasheet– On 65 nm Proce

10 Datasheet

Boxed Processor Specifications100 Datasheet § §Figure 23. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side 1 View)Figure 24. Boxed Pr

Datasheet 101Balanced Technology Extended (BTX) Boxed Processor Specifications8 Balanced Technology Extended (BTX) Boxed Processor SpecificationsThe I

Balanced Technology Extended (BTX) Boxed Processor Specifications102 DatasheetNOTE: The duct, clip, heatsink and fan can differ from this drawing repr

Datasheet 103Balanced Technology Extended (BTX) Boxed Processor SpecificationsNOTE: Diagram does not show the attached hardware for the clip design an

Balanced Technology Extended (BTX) Boxed Processor Specifications104 DatasheetNOTE: Diagram does not show the attached hardware for the clip design an

Datasheet 105Balanced Technology Extended (BTX) Boxed Processor SpecificationsSee the Support and Retention Module (SRM) External Design Requirements

Balanced Technology Extended (BTX) Boxed Processor Specifications106 DatasheetNote: The boxed processor’s TMA requires a constant +12 V supplied to pi

Datasheet 107Balanced Technology Extended (BTX) Boxed Processor Specifications8.3 Thermal SpecificationsThis section describes the cooling requirement

Balanced Technology Extended (BTX) Boxed Processor Specifications108 DatasheetIn addition, Type I TMA must be used with Type I chassis only and Type I

Datasheet 109Balanced Technology Extended (BTX) Boxed Processor SpecificationsNOTES:1. Set point variance is approximately ±1°C from Thermal Module As

Datasheet 11Introduction1 IntroductionThe Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme Edition 955, 965 are Intel’s

Balanced Technology Extended (BTX) Boxed Processor Specifications110 Datasheet

Datasheet 111Debug Tools Specifications9 Debug Tools Specifications9.1 Logic Analyzer Interface (LAI)Intel is working with two logic analyzer vendors

Debug Tools Specifications112 Datasheet

Introduction12 DatasheetThe Intel Pentium D processor 900 sequence supports Enhanced Intel® SpeedStep® technology that allows trade-offs to be made be

Datasheet 13Introduction• Intel® 975X Express chipset — Chipset that supports DDR2 memory technology for the processor.• Processor core — Processor co

Introduction14 Datasheet§ §Intel® 64 and IA-32 Intel Architecture Software Developer's ManualVolume 1: Basic Architecture http://www.intel.com/pr

Datasheet 15Electrical Specifications2 Electrical SpecificationsThis chapter describes the electrical characteristics of the processor interfaces and

Electrical Specifications16 Datasheet2.2.3 FSB DecouplingThe processor integrates signal termination on the die. In addition, some of the high frequen

Datasheet 17Electrical SpecificationsTable 2. Voltage Identification DefinitionVID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID0010

Electrical Specifications18 Datasheet2.4 Reserved, Unused, and TESTHI SignalsAll RESERVED lands must remain unconnected. Connection of these lands to

Datasheet 19Electrical Specifications2.5 Voltage and Current Specification2.5.1 Absolute Maximum and Minimum RatingsTable 3 specifies absolute maximum

2 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO AN

Electrical Specifications20 Datasheet2.5.2 DC Voltage and Current SpecificationTable 4. Voltage and Current SpecificationsSymbol Parameter Min Typ Max

Datasheet 21Electrical SpecificationsICC_RESETProcessor numberExtreme Edition 965Extreme Edition 955960950940ICC when PWRGOOD and RESET# are active fo

Electrical Specifications22 DatasheetIENHANCED_AUTO_HALTProcessor numberExtreme Edition 965Extreme Edition 955960950940ICC Enhanced Auto Halt for 775_

Datasheet 23Electrical Specifications15.This is maximum total current drawn from VTT plane by only the processor. This specification does not include

Electrical Specifications24 DatasheetNOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as sho

Datasheet 25Electrical SpecificationsNOTES:1. VOS is measured overshoot voltage.2. TOS is measured time duration above VID.2.5.4 Die Voltage Validatio

Electrical Specifications26 Datasheet2.6.1 FSB Signal GroupsThe front side bus signals have been combined into groups by buffer type. GTL+ input signa

Datasheet 27Electrical SpecificationsNOTES:1. Refer to Section 4.2 for signal descriptions.2. In processor systems where no debug port is implemented

Electrical Specifications28 Datasheet2.6.2 GTL+ Asynchronous SignalsLegacy input signals such as A20M#, IGNNE#, INIT#, PWRGOOD, SMI#, and STPCLK# use

Datasheet 29Electrical Specifications.Table 11. GTL+ Asynchronous Signal Group DC SpecificationsSymbol Parameter Min Max Unit Notes1NOTES:1. Unless ot

Datasheet 3ContentsContents1Introduction...11

Electrical Specifications30 DatasheetTable 13. VTTPWRGD DC SpecificationsSymbol Parameter Min Typ Max UnitVILInput Low Voltage — — 0.3 VVIHInput High

Datasheet 31Electrical Specifications2.6.3.1 GTL+ Front Side Bus SpecificationsIn most cases, termination resistors are not required as these are inte

Electrical Specifications32 Datasheet2.7 Clock Specifications2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor ClockingBCLK[1:0] directly controls

Datasheet 33Electrical Specifications2.7.3 Phase Lock Loop (PLL) and FilterVCCA and VCCIOPLL are power sources required by the PLL clock generators fo

Electrical Specifications34 Datasheet.NOTES:1. Diagram not to scale.2. No specification for frequencies beyond fcore (core frequency).3. fpeak, if exi

Datasheet 35Electrical Specifications2.7.4 BCLK[1:0] Specifications§ §Table 19. Front Side Bus Differential BCLK SpecificationsSymbol Parameter Min Ty

Electrical Specifications36 Datasheet

Datasheet 37Package Mechanical Specifications3 Package Mechanical SpecificationsThe processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) pac

Package Mechanical Specifications38 DatasheetFigure 5. Processor Package Drawing Sheet 1 of 3

Datasheet 39Package Mechanical SpecificationsFigure 6. Processor Package Drawing Sheet 2 of 3

4 Datasheet5.2.5 THERMTRIP# Signal...885.2.6 TCONTROL and Fan Speed Reduc

Package Mechanical Specifications40 DatasheetFigure 7. Processor Package Drawing Sheet 3 of 3

Datasheet 41Package Mechanical Specifications3.2 Processor Component Keep-Out ZonesThe processor may contain components on the substrate that define c

Package Mechanical Specifications42 Datasheet3.6 Processor Mass SpecificationThe typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight]

Datasheet 43Package Mechanical Specifications3.9 Processor Land CoordinatesFigure 10 shows the top view of the processor land coordinates. The coordin

Package Mechanical Specifications44 Datasheet.§ §Figure 10. Processor Land Coordinates and Quadrants (Top View)123456789101112131415161718192021222324

Datasheet 45Land Listing and Signal Descriptions4 Land Listing and Signal DescriptionsThis chapter provides the processor land assignment and signal d

Land Listing and Signal Descriptions46 DatasheetFigure 11. land-out Diagram (Top View – Left Side)30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15ANVCC

Datasheet 47Land Listing and Signal DescriptionsFigure 12. land-out Diagram (Top View – Right Side)14 13 12 11 10 9 8 7 6 5 4 3 2 1VCC VSS VCC VCC VSS

Land Listing and Signal Descriptions48 DatasheetTable 23. Alphabetical Land AssignmentsLand NameLand #Signal Buffer TypeDirectionA10# U6 Source Synch

Land Listing and Signal DescriptionsDatasheet 49D17# F8 Source Synch Input/OutputD18# F9 Source Synch Input/OutputD19# E9 Source Synch Input/OutputD2#

Datasheet 5Figures1VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and 775_VR_CONFIG_05B (Performance) Processors...

Land Listing and Signal Descriptions50 DatasheetDSTBP1# E12 Source Synch Input/OutputDSTBP2# G19 Source Synch Input/OutputDSTBP3# C17 Source Synch Inp

Land Listing and Signal DescriptionsDatasheet 51TESTHI1 W3 Power/Other InputTESTHI10 H5 Power/Other InputTESTHI11 P1 Power/Other InputTESTHI12 W2 Powe

Land Listing and Signal Descriptions52 DatasheetVCC AG30 Power/Other VCC AG8 Power/Other VCC AG9 Power/Other VCC AH11 Power/Other VCC AH12 Power/O

Land Listing and Signal DescriptionsDatasheet 53VCC AN12 Power/Other VCC AN14 Power/Other VCC AN15 Power/Other VCC AN18 Power/Other VCC AN19 Power

Land Listing and Signal Descriptions54 DatasheetVCC T8 Power/Other VCC U23 Power/Other VCC U24 Power/Other VCC U25 Power/Other VCC U26 Power/Other

Land Listing and Signal DescriptionsDatasheet 55VSS AB28 Power/Other VSS AB29 Power/Other VSS AB30 Power/Other VSS AB7 Power/Other VSS AC3 Power/O

Land Listing and Signal Descriptions56 DatasheetVSS AK10 Power/Other VSS AK13 Power/Other VSS AK16 Power/Other VSS AK17 Power/Other VSS AK2 Power/

Land Listing and Signal DescriptionsDatasheet 57VSS E28 Power/Other VSS E29 Power/Other VSS E8 Power/Other VSS F10 Power/Other VSS F13 Power/Other

Land Listing and Signal Descriptions58 DatasheetVSS R30 Power/Other VSS R5 Power/Other VSS R7 Power/Other VSS T3 Power/Other VSS T6 Power/Other V

Land Listing and Signal DescriptionsDatasheet 59Table 24. Numerical Land AssignmentLand #Land NameSignal Buffer TypeDirectionA10 D08# Source Synch Inp

6 DatasheetTables1 References ...132 Voltag

Land Listing and Signal Descriptions60 DatasheetAC4 RESERVED AC5 A25# Source Synch Input/OutputAC6 VSS Power/Other AC7 VSS Power/Other AC8 VCC Pow

Land Listing and Signal DescriptionsDatasheet 61AF29 VSS Power/Other AF3 VSS Power/Other AF30 VSS Power/Other AF4 A28# Source Synch Input/OutputAF5

Land Listing and Signal Descriptions62 DatasheetAJ12 VCC Power/Other AJ13 VSS Power/Other AJ14 VCC Power/Other AJ15 VCC Power/Other AJ16 VSS Power

Land Listing and Signal DescriptionsDatasheet 63AL23 VSS Power/Other AL24 VSS Power/Other AL25 VCC Power/Other AL26 VCC Power/Other AL27 VSS Power

Land Listing and Signal Descriptions64 DatasheetAN6VSS_MB_REGULATIONPower/Other OutputAN7 FC16 Power/Other OutputAN8 VCC Power/Other AN9 VCC Power/O

Land Listing and Signal DescriptionsDatasheet 65D16 RESERVED D17 D49# Source Synch Input/OutputD18 VSS Power/Other D19 DBI2# Source Synch Input/Out

Land Listing and Signal Descriptions66 DatasheetF3 BR0# Common Clock Input/OutputF4 VSS Power/Other F5 RS1# Common Clock InputF6 IMPSEL Power/Other I

Land Listing and Signal DescriptionsDatasheet 67J14 VCC Power/Other J15 VCC Power/Other J16 DP0# Common Clock Input/OutputJ17 DP3# Common Clock Inpu

Land Listing and Signal Descriptions68 DatasheetM8 VCC Power/Other N1 PWRGOOD Power/Other InputN2 IGNNE# Asynch GTL+ InputN23 VCC Power/Other N24 VC

Land Listing and Signal DescriptionsDatasheet 69U28 VCC Power/Other U29 VCC Power/Other U3 AP1# Common Clock Input/OutputU30 VCC Power/Other U4 A13

Datasheet 7Revision HistoryRevision History§ §Revision NumberDescription Date-001 • Initial release December 2005-002 • Added specifications for Intel

Land Listing and Signal Descriptions70 Datasheet4.2 Alphabetical Signals ReferenceTable 25. Signal Description (Sheet 1 of 9)Name Type DescriptionA[35

Datasheet 71Land Listing and Signal DescriptionsBCLK[1:0] InputThe differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB

Land Listing and Signal Descriptions72 DatasheetBSEL[2:0] OutputThe BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor inpu

Datasheet 73Land Listing and Signal DescriptionsDBR# OutputDBR# (Debug Reset) is used only in processor systems where no debug port is implemented on

Land Listing and Signal Descriptions74 DatasheetFERR#/PBE# OutputFERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its

Datasheet 75Land Listing and Signal DescriptionsINIT# InputINIT# (Initialization), when asserted, resets integer registers inside the processor withou

Land Listing and Signal Descriptions76 DatasheetMSID[1:0] InputMSID[1:0] (input) MSID0 is used to indicate to the processor whether the platform suppo

Datasheet 77Land Listing and Signal DescriptionsRSP# InputRSP# (Response Parity) is driven by the response agent (the agent responsible for completion

Land Listing and Signal Descriptions78 DatasheetTHERMTRIP# OutputIn the event of a catastrophic cooling failure, the processor will automatically shut

Datasheet 79Land Listing and Signal Descriptions§ §VSS_SENSE OutputVSS_SENSE is an isolated low impedance connection to processor core VSS. It can be

8 Datasheet

Land Listing and Signal Descriptions80 Datasheet

Datasheet 81Thermal Specifications and Design Considerations5 Thermal Specifications and Design Considerations5.1 Processor Thermal SpecificationsThe

Thermal Specifications and Design Considerations82 DatasheetPentium® Processor Extreme Edition, and Intel® Pentium® 4 Processor Thermal and Mechanical

Datasheet 83Thermal Specifications and Design ConsiderationsTable 27. Thermal Profile for 775_VR_CONFIG_05B Processors (Performance)Power (W)Maximum T

Thermal Specifications and Design Considerations84 DatasheetTable 28. Thermal Profile for 775_VR_CONFIG_05A Processors (Mainstream)Power (W)Maximum TC

Datasheet 85Thermal Specifications and Design Considerations5.1.2 Thermal MetrologyThe maximum and minimum case temperatures (TC) for the processor is

Thermal Specifications and Design Considerations86 Datasheetperiods of TCC activation is expected to be so minor that it would be immeasurable. An und

Datasheet 87Thermal Specifications and Design ConsiderationsAs a bi-directional signal, PROCHOT# allows for some protection of various components from

Thermal Specifications and Design Considerations88 Datasheet5.2.5 THERMTRIP# SignalRegardless of whether or not Thermal Monitor is enabled, in the eve

Datasheet 89Thermal Specifications and Design Considerations5. The series resistance, RT, is provided to allow for a more accurate measurement of the

Datasheet 9Intel® Pentium® D Processor 900 Sequence and Intel® Pentium® Processor Extreme Edition 955, 965 FeaturesThe Intel® Pentium® D processor 900

Thermal Specifications and Design Considerations90 Datasheetcalculated. This Thermal Diode Offset value will be programmed into the new diode correcti

Datasheet 91Features6 Features6.1 Power-On Configuration OptionsSeveral configuration options can be configured by hardware. The processor samples the

Features92 Datasheet6.2.1 Normal StateThis is the normal operating state for the processor.6.2.2 HALT and Enhanced HALT Powerdown StatesThe processor

Datasheet 93FeaturesThe return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Int

Features94 Datasheet6.2.4 Enhanced HALT Snoop or HALT Snoop State,Stop Grant Snoop StateThe Enhanced HALT Snoop State is used in conjunction with the

Datasheet 95Boxed Processor Specifications7 Boxed Processor SpecificationsThe Intel Pentium D processor 900 sequence and the Intel Pentium processor E

Boxed Processor Specifications96 DatasheetClearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical s

Datasheet 97Boxed Processor Specifications7.1.2 Boxed Processor Fan Heatsink WeightThe boxed processor fan heatsink will not weigh more than 550 grams

Boxed Processor Specifications98 DatasheetThe power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The

Datasheet 99Boxed Processor Specifications7.3 Thermal SpecificationsThis section describes the cooling requirements of the fan heatsink solution used