Intel i7-4770K Manuale Utente Pagina 1

Desktop 4th Generation Intel® Core™Processor Family, Desktop Intel®Pentium® Processor Family, andDesktop Intel® Celeron® ProcessorFamilyDatasheet – Vo

1.0 IntroductionThe Desktop 4th Generation Intel® Core™ processor family , Desktop Intel® Pentium®processor family, and Desktop Intel® Celeron® proce

Table 49. VCCIO_OUT, VCOMP_OUT, and VCCIO_TERMSymbol Parameter Typ Max Units NotesVCCIO_OUTTerminationVoltage1.0 — VICCIO_OUTMaximumExternal Load— 300

Symbol Parameter Min Typ Max Units Notes1RON_DN(CTL)DDR3/DDR3L ControlBuffer pull-downResistance19 25 31 Ω5, 11,13RON_UP(RST)DDR3/DDR3L ResetBuffer pu

Table 52. embedded DisplayPort* (eDP*) Group DC SpecificationsSymbol Parameter Min Typ Max UnitsVILHPD Input Low Voltage 0.02 — 0.21 VVIHHPD Input Hig

Symbol Parameter Min Max Units Notes1VIHInput High Voltage (other GTL) VCCIO_TERM * 0.72 — V 2, 4RONBuffer on Resistance (CFG/BPM) 16 24 Ω —RONBuffer

Symbol Definition and Conditions Min Max Units Notes1VnNegative-Edge ThresholdVoltage0.275 *VCCIO_TERM0.500* VCCIO_TERMV —VpPositive-Edge ThresholdVol

8.0 Package Mechanical SpecificationsThe processor is packaged in a Flip-Chip Land Grid Array package that interfaces withthe motherboard using the L

mechanical system or component testing should not exceed the maximum limits. Theprocessor package substrate should not be used as a mechanical referen

Table 59. Processor MaterialsComponent MaterialIntegrated Heat Spreader (IHS) Nickel Plated CopperSubstrate Fiber Reinforced ResinSubstrate Lands Gold

Figure 26. Processor Package Land CoordinatesProcessor Storage SpecificationsThe following table includes a list of the specifications for device stor

Parameter Description Minimum Maximum NotesRHsustained storageThe maximum device storage relativehumidity for a sustained period of time.60% @ 24 °C 5

Figure 1. Platform Block DiagramProcessorPCI Express* 3.0Digital Display Interface (DDI)(3 interfaces) System Memory1333 / 1600 MT/s 2 DIMMs / CHCH AC

9.0 Processor Ball and Signal InformationThis chapter provides processor ball information. The following table provides the balllist by signal name.N

Signal Name Ball #DPLL_REF_CLKN W6DPLL_REF_CLKP W5EDP_DISP_UTIL E16FC_K9 K9FC_Y7 Y7FDI_CSYNC D16FDI0_TX0N0 B14FDI0_TX0N1 C13FDI0_TX0P0 A14FDI0_TX0P1 B

Signal Name Ball #RSVD J17RSVD J40RSVD J9RSVD L10RSVD L12RSVD M10RSVD M11RSVD M38RSVD N35RSVD P33RSVD R33RSVD R34RSVD T34RSVD T35RSVD T8RSVD U8RSVD W8

Signal Name Ball #SA_DQ53 AL3SA_DQ54 AJ2SA_DQ55 AJ1SA_DQ56 AG1SA_DQ57 AG4SA_DQ58 AE3SA_DQ59 AE4SA_DQ6 AF37SA_DQ60 AG2SA_DQ61 AG3SA_DQ62 AE2SA_DQ63 AE1

Signal Name Ball #SB_DQ3 AH35SB_DQ30 AP29SB_DQ31 AP28SB_DQ32 AR12SB_DQ33 AP12SB_DQ34 AL13SB_DQ35 AL12SB_DQ36 AR13SB_DQ37 AP13SB_DQ38 AM13SB_DQ39 AM12S

Signal Name Ball #VCC A24VCC A25VCC A26VCC A27VCC A28VCC A29VCC A30VCC B25VCC B27VCC B29VCC B31VCC B33VCC B35VCC C24VCC C25VCC C26VCC C27VCC C28VCC C2

Signal Name Ball #VCC L28VCC L29VCC L30VCC L31VCC L32VCC L33VCC L34VCC M13VCC M15VCC M17VCC M19VCC M21VCC M23VCC M25VCC M27VCC M29VCC M33VCC M8VCC P8V

Signal Name Ball #VSS AG40VSS AG5VSS AG8VSS AH1VSS AH2VSS AH3VSS AH33VSS AH36VSS AH4VSS AH5VSS AH8VSS AJ11VSS AJ14VSS AJ16VSS AJ18VSS AJ19VSS AJ22VSS

Signal Name Ball #VSS AP24VSS AP27VSS AP30VSS AP36VSS AP4VSS AP5VSS AR11VSS AR14VSS AR16VSS AR17VSS AR18VSS AR19VSS AR20VSS AR21VSS AR22VSS AR23VSS AR

Signal Name Ball #VSS C6VSS D11VSS D13VSS D15VSS D17VSS D2VSS D23VSS D24VSS D26VSS D28VSS D30VSS D32VSS D34VSS D36VSS D37VSS D5VSS D6VSS D7VSS D9VSS E

• PCLMULQDQ Instruction• Intel® Secure Key• Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)• PAIR – Power Aware Int

Signal Name Ball #VSS K40VSS K7VSS L11VSS L13VSS L14VSS L3VSS L35VSS L36VSS L38VSS L6VSS L7VSS L8VSS L9VSS M1VSS M12VSS M14VSS M16VSS M18VSS M20VSS M2

Thermal Management Support• Digital Thermal Sensor• Adaptive Thermal Monitor• THERMTRIP# and PROCHOT# support• On-Demand Mode• Memory Open and Closed

Term DescriptionECC Error Correction CodeeDP* embedded DisplayPort*EPG Electrical Power GatingEU Execution UnitFMA Floating-point fused Multiply Add i

Term DescriptionMLC Mid-Level CacheMSI Message Signaled InterruptMSL Moisture Sensitive LabelingMSR Model Specific RegistersNCTFNon-Critical to Functi

Term DescriptionTAP Test Access PointTCASEThe case temperature of the processor, measured at the geometric center of the top-side of the TTV IHS.TCC T

Document DocumentNumber / LocationLGA1150 Socket Application Guide 328999Intel® 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH)Dat

2.0 InterfacesSystem Memory Interface• Two channels of DDR3/DDR3L Unbuffered Dual In-Line Memory Modules (UDIMM)or DDR3/DDR3L Unbuffered Small Outlin

System Memory Technology SupportedThe Integrated Memory Controller (IMC) supports DDR3/DDR3L protocols with twoindependent, 64-bit wide channels each

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OROTHERWISE, TO ANY INTELLECTU

RawCardVersionDIMMCapacityDRAMDeviceTechnologyDRAMOrganization# ofDRAMDevices# ofPhysicalDevicesRanks# ofRow / ColAddressBits# ofBanksInsideDRAMPage S

Note: System memory timing support is based on availability and is subject to change.System Memory Organization ModesThe Integrated Memory Controller

be on opposite channels. Use Dual-Channel Symmetric mode when both Channel Aand Channel B DIMM connectors are populated in any order, with the total a

Data ScramblingThe system memory controller incorporates a Data Scrambling feature to minimize theimpact of excessive di/dt on the platform system mem

• PCI Express* extended configuration space. The first 256 bytes of configurationspace aliases directly to the PCI Compatibility configuration space.

Figure 3. PCI Express* Related Register Structures in the ProcessorPCI-PCI Bridge representing root PCI Express ports (Device 1 and Device 6)PCI Compa

Figure 4. PCI Express* Typical Operation 16 Lanes Mapping01234567891011121314151 X 16ControllerLane 00123456789101112131415Lane 1Lane 2Lane 3Lane 4Lan

• 5 GT/s point-to-point DMI interface to PCH is supported.• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of500 MB

Processor GraphicsThe processor graphics contains a generation 7.5 graphics core architecture. Thisenables substantial gains in performance and lower

Figure 5. Processor Graphics Controller Unit Block Diagram3D and Video Engines for Graphics ProcessingThe Gen 7.5 3D engine provides the following per

ContentsRevision History...91.0 Introdu

Vertex Shader (VS) StageThe VS stage performs shading of vertices output by the VF function. The VS unitproduces an output vertex reference for every

Logical 128-Bit Fixed BLT and 256 Fill EngineThis BLT engine accelerates the GUI of Microsoft Windows* operating systems. The128-bit BLT engine provid

• The HDMI* interface supports HDMI with 3D, 4K, Deep Color, and x.v.Color. TheDisplayPort* interface supports the VESA DisplayPort* Standard Version

• Organizing pixels into frames• Optionally scaling the image to the desired size• Re-timing data for the intended target• Formatting data according t

make up the TMDS data and clock channels. These channels are used to carry video,audio, and auxiliary data. In addition, HDMI carries a VESA DDC. The

embedded DisplayPort*embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort standardoriented towards applications such as notebook and

Table 9. Valid Three Display Configurations through the ProcessorDisplay 1 Display 2 Display 3 MaximumResolution Display1MaximumResolutionDisplay 2Max

Intel® Flexible Display Interface (Intel® FDI)• The Intel Flexible Display Interface (Intel FDI) passes display data from theprocessor (source) to the

Figure 9. PECI Host-Clients Connection ExampleVTTHost / OriginatorQ1nXQ21XPECICPECI<10pF/NodeQ3nXVTTPECI ClientAdditional PECI ClientsProcessor—Int

3.0 TechnologiesThis chapter provides a high-level description of Intel technologies implemented in theprocessor.The implementation of the features m

4.2.3 Requesting Low-Power Idle States...534.2.4 Core C-State Rules...

• More reliable: Due to the hardware support, VMMs can now be smaller, lesscomplex, and more efficient. This improves reliability and availability and

• Descriptor-Table Exiting— Descriptor-table exiting allows a VMM to protect a guest operating systemfrom an internal (malicious software based) attac

Figure 10. Device to Domain Mapping StructuresRoot entry 0Root entry NRoot entry 255Context entry 0Context entry 255Context entry 0Context entry 255(B

• Memory controller and processor graphics comply with the Intel VT-d 1.2Specification• Two Intel VT-d DMA remap engines— iGFX DMA remap engine— Defau

Another aspect of the trust decision is the ability of the platform to resist attempts tochange the controlling environment. The Intel TXT platform wi

Intel recommends enabling Intel HT Technology with Microsoft Windows* 8 andMicrosoft Windows* 7 and disabling Intel HT Technology using the BIOS for a

digital signal processing software. FMA improves performance in face detection,professional imaging, and high performance computing. Gather operations

extensions to achieve the performance of fine-grain locking while actuallyprogramming using coarse-grain locks. Details on Intel TSX-NI are in the Int

• The semantics for accessing APIC registers have been revised to simplify theprogramming of frequently-used APIC registers by system software. Specif

4.0 Power ManagementThis chapter provides information on the following power management topics:• Advanced Configuration and Power Interface (ACPI) St

7.0 Electrical Specifications... 907.1 Integrated Voltage R

Advanced Configuration and Power Interface (ACPI)States SupportedThis section describes the ACPI states supported by the processor.Table 11. System St

Table 15. Direct Media Interface (DMI) StatesState DescriptionL0 Full on – Active transfer state.L0s First Active Power Management low-power state – L

• Multiple frequency and voltage points for optimal performance and powerefficiency. These operating points are known as P-states.• Frequency selectio

Figure 13. Thread and Core C-State Entry and ExitC1 C1E C7C6C3C0MWAIT(C1), HLTC0MWAIT(C7),P_LVL4 I/O ReadMWAIT(C6),P_LVL3 I/O ReadMWAIT(C3),P_LVL2 I/O

Note: When P_LVLx I/O instructions are used, MWAIT sub-states cannot be defined. TheMWAIT sub-state is always zero if I/O MWAIT redirection is used.

Core C6 StateIndividual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read oran MWAIT(C6) instruction. Before entering core C6 s

— For package C-states, the processor is not required to enter C0 state beforeentering any other C-state.— Entry into a package C-state may be subject

Figure 14. Package C-State Entry and ExitC0C1C6C7C3Package C0 StateThis is the normal operating state for the processor. The processor remains in then

Package C2 StatePackage C2 state is an internal processor state that cannot be explicitly requested bysoftware. A processor enters Package C2 state wh

Note: Package C6 state is the deepest C-state supported on discrete graphics systems withPCI Express Graphics (PEG).Package C7 state is the deepest C

Figures1 Platform Block Diagram ... 112 Intel® Flex Memory Tec

Number of Displays 1Native Resolution Deepest Available Package C-StateSingle 2880x1620 60 Hz PC3Single 2880x1800 60 Hz PC3Single 3200x1800 60 Hz PC3S

• Reduced possible overshoot/undershoot signal quality issues seen by theprocessor I/O buffer receivers caused by reflections from potentially un-term

Selection of power modes should be according to power-performance or thermaltrade-offs of a given system:• When trying to achieve maximum performance

assertion with all pages closed). Pre-charge power-down provides greater powersavings, but has a bigger performance impact since all pages will first

Graphics Power ManagementIntel® Rapid Memory Power Management (Intel® RMPM)Intel Rapid Memory Power Management (Intel RMPM) conditionally places memor

5.0 Thermal ManagementThis chapter provides both component-level and system-level thermal management.Topics covered include processor thermal specifi

Table 21. Desktop Processor Thermal SpecificationsProduct PCG8MaxPowerPackage C1E(W) 1, 2,5, 9MaxPowerPackage C3(W) 1, 3,5, 9MinPowerPackageC3 (W)9Max

Processor (PCG 2013D) Thermal ProfileFigure 15. Thermal Test Vehicle Thermal Profile for Processor (PCG 2013D)4045505560657075800 20 40 60 80 100TTV C

Processor (PCG 2013C) Thermal ProfileFigure 16. Thermal Test Vehicle Thermal Profile for Processor (PCG 2013C)See the following table for discrete poi

Power (W) TCASE_MAX (°C)62 70.1264 70.9465 71.35Processor (PCG 2013B) Thermal ProfileFigure 17. Thermal Test Vehicle Thermal Profile for Processor (PC

Tables1 Terminology... 132 Related Documents..

Processor (PCG 2013A) Thermal ProfileFigure 18. Thermal Test Vehicle Thermal Profile for Processor (PCG 2013A)See the following table for discrete poi

Thermal MetrologyThe maximum Thermal Test Vehicle (TTV) case temperatures (TCASE-MAX) can bederived from the data in the appropriate TTV thermal profi

The ΨCA point at DTS = -1 defines the minimum ΨCA required at TDP considering theworst case system design TAMBIENT design point:ΨCA = (TCASE-MAX – TAM

Table 26. Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance AboveTCONTROLProcessorTDPΨCA at DTS =TCONTROL1, 2At System TAMBIENT-MAX = 30 °

Figure 21. Digital Thermal Sensor (DTS) Thermal Profile DefinitionTable 27. Thermal Margin SlopePCG DieConfiguration(Native)Core + GTTDP (W) TCC Activ

Adaptive Thermal MonitorThe Adaptive Thermal Monitor feature provides an enhanced method for controllingthe processor temperature when the processor s

after 1 ms the processor is still too hot (the temperature has not dropped below theTCC activation point, DTS still = 0 and PROCHOT is still active),

If TM1 and TM2 have both been active for greater than 20 ms and the processortemperature has not dropped below the TCC activation point, the Critical

a backup in case of system cooling failure. The system thermal design should allowthe power delivery circuitry to operate within its temperature speci

have the capability of generating interrupts using the core's local APIC. Refer to theIntel® 64 and IA-32 Architectures Software Developer’s Manu

54 GTL Signal Group and Open Drain Signal Group DC Specifications... 10255 PCI Express* DC Specifications...

• Uncharacterized workloads may exist that could result in higher turbo frequenciesand power. If that were to happen, the processor Thermal Control Ci

Figure 22. Package Power ControlTurbo Time ParameterTurbo Time Parameter is a mathematical parameter (units in seconds) that controlsthe Intel Turbo B

6.0 Signal DescriptionThis chapter describes the processor signals. The signals are arranged in functionalgroups according to the associated interfac

Signal Name Description Direction / BufferTypeSA_RAS#RAS Control Signal: This signal is used with SA_CAS# andSA_WE# (along with SA_CS#) to define the

Signal Name Description Direction / BufferTypeSB_CK[3:0]SDRAM Differential Clock: Channel B SDRAM Differentialclock signal pair. The crossing of the p

Reset and Miscellaneous SignalsTable 33. Reset and Miscellaneous SignalsSignal Name Description Direction /Buffer TypeCFG[19:0]Configuration Signals:

PCI Express*-Based Interface SignalsTable 34. PCI Express* Graphics Interface SignalsSignal Name Description Direction / Buffer TypePEG_RCOMPPCI Expre

Phase Locked Loop (PLL) SignalsTable 37. Phase Locked Loop (PLL) SignalsSignal Name Description Direction / BufferTypeBCLKPBCLKNDifferential bus clock

Error and Thermal Protection SignalsTable 39. Error and Thermal Protection SignalsSignal Name Description Direction / BufferTypeCATERR#Catastrophic Er

Processor Power SignalsTable 41. Processor Power SignalsSignal Name Description Direction / BufferTypeVCC Processor core power rail. RefVCCIO_OUT Proc

Revision HistoryRevision Description Date001 • Initial Release June 2013002• Added Desktop 4th Generation Intel® Core™ i7-4771, i5-4440,i5-4440S, i3-4

7.0 Electrical SpecificationsThis chapter provides the processor electrical specifications including integratedvoltage regulator (VR), VCC Voltage Id

Table 45. Voltage Regulator (VR) 12.5 Voltage IdentificationBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex VCC0 0 0 0 0 0 0 0 00h 0.00000 0 0 0 0 0 0 1 01h 0.500

Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex VCC0 1 0 0 0 0 1 0 42h 1.15000 1 0 0 0 0 1 1 43h 1.16000 1 0 0 0 1 0 0 44h 1.17000 1 0 0 0 1 0 1 45h 1.18000 1 0 0

Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex VCC1 0 0 0 0 1 1 0 86h 1.83001 0 0 0 0 1 1 1 87h 1.84001 0 0 0 1 0 0 0 88h 1.85001 0 0 0 1 0 0 1 89h 1.86001 0 0 0

Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex VCC1 1 0 0 1 0 1 0 CAh 2.51001 1 0 0 1 0 1 1 CBh 2.52001 1 0 0 1 1 0 0 CCh 2.53001 1 0 0 1 1 0 1 CDh 2.54001 1 0 0

Reserved or Unused SignalsThe following are the general types of reserved (RSVD) signals and connectionguidelines:• RSVD – these signals should not be

Signal Group Type SignalsDDR3 / DDR3L Data Signals 2Single ended DDR3/DDR3L Bi-directionalSA_DQ[63:0], SB_DQ[63:0]Differential DDR3/DDR3L Bi-direction

Signal Group Type SignalsTest Point RSVD_TPOther SKTOCC#, PCI Express* GraphicsDifferential PCI Express Input PEG_RXP[15:0], PEG_RXN[15:0]Differential

• AC tolerances for all DC rails include dynamic load currents at switchingfrequencies up to 1 MHz.Voltage and Current SpecificationsTable 47. Process

Symbol Parameter Min Typ Max Unit Note1ICC2013A PCGICC— — 48 A 4, 8PMAX2013D PCGPMAX— — 153 W 9PMAX2013C PCGPMAX— — 121 W 9PMAX2013B PCGPMAX— — 99 W 9