Intel Webcam 253668-032US manuali

Intel Webcam 253668-032US Manuale Utente (806 pagine)

Marchio: Intel | Categoria: Processori | Dimensione: 5.71 MB |

Indice

Software Developer’s Manual

Vol. 3A

CONTENTS

CHAPTER 1

ABOUT THIS MANUAL

1-2 Vol. 3

Vol. 3 1-3

1-4 Vol. 3

Vol. 3 1-5

1.3 NOTATIONAL CONVENTIONS

1.3.3 Instruction Operands

1.3.5 Segmented Addressing

Vol. 3 1-9

1.3.7 Exceptions

Vol. 3 1-11

1-12 Vol. 3

CHAPTER 2

SYSTEM ARCHITECTURE OVERVIEW

2-2 Vol. 3

Vol. 3 2-5

2-6 Vol. 3

Vol. 3 2-7

2.1.5 Memory Management

2.1.6 System Registers

2.1.7 Other System Resources

Management

2-14 Vol. 3

Vol. 3 2-15

2.5 CONTROL REGISTERS

2-18 Vol. 3

OSXMMEXCPT

2-20 Vol. 3

Vol. 3 2-21

2-22 Vol. 3

Vol. 3 2-23

2-24 Vol. 3

Vol. 3 2-25

Vol. 3 2-27

2-28 Vol. 3

Vol. 3 2-29

2-30 Vol. 3

Vol. 3 2-31

2-32 Vol. 3

Vol. 3 2-33

CHAPTER 3

Logical Address

Linear Address

3.2 USING SEGMENTS

3.2.2 Protected Flat Model

3.2.3 Multi-Segment Model

3.3 PHYSICAL ADDRESS SPACE

3.3.1 Intel

3.4.2 Segment Selectors

3.4.3 Segment Registers

100

3-12 Vol. 3

102

3.4.5 Segment Descriptors

103

3-14 Vol. 3

104

Vol. 3 3-15

105

3-16 Vol. 3

106

Vol. 3 3-17

107

3.5 SYSTEM DESCRIPTOR TYPES

108

• Call-gate descriptor

109

• Interrupt-gate descriptor

109

• Trap-gate descriptor

109

• Task-gate descriptor

109

Vol. 3 3-21

111

CHAPTER 4

113

4.1.1 Three Paging Modes

114

4.1.2 Paging-Mode Enabling

115

4.1.3 Paging-Mode Modifiers

117

4-6 Vol. 3

118

Vol. 3 4-7

119

4.3 32-BIT PAGING

120

Vol. 3 4-9

121

Page Directory

122

4-12 Vol. 3

124

Vol. 3 4-13

125

4-14 Vol. 3

126

4.4 PAE PAGING

127

4.4.1 PDPTE Registers

128

Vol. 3 4-17

129

Vol. 3 4-19

131

4-20 Vol. 3

132

Vol. 3 4-21

133

4-22 Vol. 3

134

4.5 IA-32E PAGING

135

4-24 Vol. 3

136

PDE with PS=0

137

PDE with PS=1

138

Directory-Pointer Table

139

References a Page Directory

140

Vol. 3 4-29

141

4-30 Vol. 3

142

Vol. 3 4-31

143

4-32 Vol. 3

144

4.7 PAGE-FAULT EXCEPTIONS

146

• P flag (bit 0)

146

• W/R (bit 1)

146

• U/S (bit 2)

146

• RSVD flag (bit 3)

147

• I/D flag (bit 4)

147

4.8 ACCESSED AND DIRTY FLAGS

148

4.9 PAGING AND MEMORY TYPING

149

4-38 Vol. 3

150

• 32-bit paging:

151

• PAE paging:

151

• IA-32e paging:

151

4.10.1.3 Details of TLB Use

152

4.10.1.4 Global Pages

153

4-42 Vol. 3

154

Vol. 3 4-43

155

4-44 Vol. 3

156

Vol. 3 4-45

157

4-46 Vol. 3

158

Vol. 3 4-47

159

4-48 Vol. 3

160

Processors

161

4-50 Vol. 3

162

EXTENSIONS (VMX)

163

4-52 Vol. 3

164

4-54 Vol. 3

166

CHAPTER 5

167

PROTECTION

167

5-2 Vol. 3

168

Vol. 3 5-3

169

Vol. 3 5-5

171

5.3 LIMIT CHECKING

172

5.4 TYPE CHECKING

173

• The type field

173

5-8 Vol. 3

174

5.5 PRIVILEGE LEVELS

175

Figure 5-3. Protection Rings

176

SEGMENTS

177

5-14 Vol. 3

180

5-16 Vol. 3

182

From Various Privilege Levels

183

• Call gates

184

• Trap gates

184

• Interrupt gates

184

• Task gates

184

5.8.3 Call Gates

185

5-20 Vol. 3

186

in Segment 15:00

187

Segment Selector

188

5-24 Vol. 3

190

5.8.5 Stack Switching

191

5-26 Vol. 3

192

5-28 Vol. 3

194

Vol. 3 5-29

195

5-30 Vol. 3

196

Vol. 3 5-31

197

5-32 Vol. 3

198

• EFLAGS — Loaded from R11

199

5.9 PRIVILEGED INSTRUCTIONS

199

5-34 Vol. 3

200

Vol. 3 5-35

201

Instruction)

202

Vol. 3 5-37

203

5.11 PAGE-LEVEL PROTECTION

205

5.11.1 Page-Protection Flags

206

5.11.3 Page Type

206

Vol. 3 5-41

207

5-42 Vol. 3

208

• IA-32e mode

209

5-44 Vol. 3

210

5.13.3 Reserved Bit Checking

211

Capability Enabled

212

• IA32_EFER.NXE = 1

213

CHAPTER 6

215

6.3 SOURCES OF INTERRUPTS

216

Vol. 3 6-3

217

6-4 Vol. 3

218

6.4 SOURCES OF EXCEPTIONS

219

• Machine-check exceptions

219

6.5 EXCEPTION CLASSIFICATIONS

220

6.6 PROGRAM OR TASK RESTART

221

6-8 Vol. 3

222

6.7.1 Handling Multiple NMIs

223

6-10 Vol. 3

224

INTERRUPTS

225

6-12 Vol. 3

226

Vol. 3 6-13

227

6.11 IDT DESCRIPTORS

228

Vol. 3 6-17

231

Vol. 3 6-19

233

6.12.2 Interrupt Tasks

234

6.13 ERROR CODE

235

Figure 6-6. Error Code

236

• IRET behavior changes

237

6-24 Vol. 3

238

6.14.3 IRET in IA-32e Mode

239

Vol. 3 6-27

241

Exception Class Fault

242

Vol. 3 6-29

243

Interrupt 2—NMI Interrupt

244

Exception Class Trap

245

Description

245

Exception Error Code

245

Saved Instruction Pointer

245

Program State Change

245

Exception Class Abort

252

6-40 Vol. 3

254

Vol. 3 6-41

255

Vol. 3 6-43

257

Vol. 3 6-45

259

Vol. 3 6-53

267

Vol. 3 6-57

271

Vol. 3 6-63

277

Not applicable

281

6-68 Vol. 3

282

CHAPTER 7

283

TASK MANAGEMENT

283

7.1.2 Task State

284

7.1.3 Executing a Task

285

7-4 Vol. 3

286

7-6 Vol. 3

288

7.2.2 TSS Descriptor

289

7-8 Vol. 3

290

7.2.4 Task Register

291

Figure 7-5. Task Register

292

7.2.5 Task-Gate Descriptor

293

7.3 TASK SWITCHING

294

Vol. 3 7-13

295

7-14 Vol. 3

296

Vol. 3 7-15

297

7.4 TAS K LIN KIN G

298

Figure 7-8. Nested Tasks

299

7-18 Vol. 3

300

7.5 TASK ADDRESS SPACE

301

Vol. 3 7-21

303

Vol. 3 7-23

305

CHAPTER 8

307

MULTIPLE-PROCESSOR MANAGEMENT

307

8-2 Vol. 3

308

8.1.2 Bus Locking

309

8.1.2.1 Automatic Locking

310

Vol. 3 8-5

311

8-6 Vol. 3

312

Vol. 3 8-7

313

8.2 MEMORY ORDERING

314

Vol. 3 8-9

315

Vol. 3 8-11

317

8-12 Vol. 3

318

Locations

319

8-14 Vol. 3

320

Vol. 3 8-15

321

8-16 Vol. 3

322

Vol. 3 8-17

323

8-18 Vol. 3

324

Operations

325

8-20 Vol. 3

326

Vol. 3 8-21

327

8-22 Vol. 3

328

Vol. 3 8-23

329

8.3 SERIALIZING INSTRUCTIONS

330

Vol. 3 8-25

331

8-26 Vol. 3

332

8.4.1 BSP and AP Processors

333

8-28 Vol. 3

334

Vol. 3 8-29

335

8-30 Vol. 3

336

Vol. 3 8-31

337

8-32 Vol. 3

338

Vol. 3 8-33

339

Vol. 3 8-35

341

8-36 Vol. 3

342

Vol. 3 8-37

343

8.7 INTEL

344

HYPER-THREADING TECHNOLOGY

344

ARCHITECTURE

344

Technology

345

8.7.2 APIC Functionality

346

Vol. 3 8-41

347

8.7.8 IA32_MISC_ENABLE MSR

348

8.7.9 Memory Ordering

348

• Caches

349

8.7.13.3 Thermal Monitor

350

Vol. 3 8-45

351

8.8 MULTI-CORE ARCHITECTURE

352

8.8.4 IA32_MISC_ENABLE MSR

353

8-48 Vol. 3

354

8-50 Vol. 3

356

Vol. 3 8-51

357

8-52 Vol. 3

358

Vol. 3 8-53

359

8-54 Vol. 3

360

Vol. 3 8-55

361

8-56 Vol. 3

362

Vol. 3 8-57

363

8-58 Vol. 3

364

Vol. 3 8-59

365

8-60 Vol. 3

366

Vol. 3 8-61

367

8-62 Vol. 3

368

Vol. 3 8-63

369

8.10.1 HLT Instruction

370

8.10.2 PAUSE Instruction

371

8-66 Vol. 3

372

Vol. 3 8-67

373

8-68 Vol. 3

374

Vol. 3 8-69

375

8-70 Vol. 3

376

Vol. 3 8-71

377

Execution Resources

378

Vol. 3 8-73

379

CHAPTER 9

381

383

Xeon Processor

383

9.2 X87 FPU INITIALIZATION

386

Vol. 3 9-7

387

9.3 CACHE ENABLING

388

Vol. 3 9-9

389

MODE OPERATION

390

OPERATION

391

9-12 Vol. 3

392

9.8.3 Initializing Paging

393

9-14 Vol. 3

394

Vol. 3 9-15

395

9-16 Vol. 3

396

9.9 MODE SWITCHING

397

9-18 Vol. 3

398

Vol. 3 9-19

399

9-20 Vol. 3

400

FFFF FFFFH

401

FFFF FFF0H

401

FFFF 0000H

401

64K EPROM

401

9.10.1 Assembler Usage

402

9.10.2 STARTUP.ASM Listing

403

9-24 Vol. 3

404

Vol. 3 9-25

405

9-26 Vol. 3

406

Vol. 3 9-27

407

9-28 Vol. 3

408

Vol. 3 9-29

409

9-30 Vol. 3

410

162-172 of List File)

411

RAM_START

412

9.10.3 MAIN.ASM Source Code

413

9.10.4 Supporting Files

414

9.11.1 Microcode Update

417

9-40 Vol. 3

420

Vol. 3 9-41

421

9-42 Vol. 3

422

Table 9-10. Processor Flags

423

9-44 Vol. 3

424

Vol. 3 9-45

425

9-46 Vol. 3

426

Vol. 3 9-47

427

9-48 Vol. 3

428

Vol. 3 9-49

429

9-50 Vol. 3

430

Vol. 3 9-51

431

9-52 Vol. 3

432

Vol. 3 9-53

433

9-54 Vol. 3

434

Vol. 3 9-55

435

9-56 Vol. 3

436

Vol. 3 9-57

437

Vol. 3 9-59

439

9-60 Vol. 3

440

Vol. 3 9-61

441

9-62 Vol. 3

442

Table 9-16. Mnemonic Values

443

9.11.8.9 Return Codes

444

Vol. 3 9-65

445

9-66 Vol. 3

446

CHAPTER 10

447

ADVANCED PROGRAMMABLE

447

INTERRUPT CONTROLLER (APIC)

447

10-2 Vol. 3

448

3-Wire APIC Bus

449

Multiple-Processor

450

Systems

450

Multiple-Processor Systems

450

10.2 SYSTEM BUS VS. APIC BUS

451

10.3 THE INTEL

451

82489DX EXTERNAL APIC

451

10.4 LOCAL APIC

452

10-8 Vol. 3

454

Vol. 3 10-9

455

10-10 Vol. 3

456

Vol. 3 10-11

457

10.4.6 Local APIC ID

458

10.4.7 Local APIC State

459

10-14 Vol. 3

460

Vol. 3 10-15

461

63 071011 8912

463

10-18 Vol. 3

464

Vol. 3 10-19

465

10-20 Vol. 3

466

Vol. 3 10-21

467

10-22 Vol. 3

468

Vol. 3 10-23

469

10.5.6.1 x2APIC States

470

Vol. 3 10-25

471

EN=1, Extd=1

472

Extended

472

EN=1, Extd=0

472

Disabled

472

Vol. 3 10-27

473

• the local APIC unit

474

Vol. 3 10-29

475

10.6.1 Local Vector Table

476

10-32 Vol. 3

478

Vol. 3 10-33

479

10.6.3 Error Handling

480

Table 10-5. ESR Flags

481

10.6.4 APIC Timer

482

10-38 Vol. 3

484

10-40 Vol. 3

486

Vol. 3 10-41

487

10-42 Vol. 3

488

Vol. 3 10-43

489

10-44 Vol. 3

490

10-46 Vol. 3

492

Vol. 3 10-47

493

ReservedLogical APIC ID

493

Address: 0FEE0 00D0H

493

Value after reset: 0000 0000H

493

Vol. 3 10-49

495

MSR Address: 80DH

495

Logical x2APIC ID

495

10-50 Vol. 3

496

← TPR[7:0]

497

10.7.4 SELF IPI Register

498

Vol. 3 10-53

499

MSR Address: 083FH

499

Reserved

499

10.9 HANDLING INTERRUPTS

500

Pentium Processors)

502

vector / 16

503

Figure 10-29. EOI Register

507

Figure 10-30. CR8 Register

508

10.10 SPURIOUS INTERRUPT

509

10.11.1 Bus Message Formats

511

10-66 Vol. 3

512

31 20 19 12 11 4 3 2 1 0

512

Vol. 3 10-67

513

31 16 15 14 13 11 10 8 7 0

513

10-68 Vol. 3

514

CHAPTER 11

515

MEMORY CACHE CONTROL

515

Vol. 3 11-3

517

11-4 Vol. 3

518

Vol. 3 11-5

519

11-6 Vol. 3

520

11.2 CACHING TERMINOLOGY

521

11-8 Vol. 3

522

Vol. 3 11-9

523

11-10 Vol. 3

524

Vol. 3 11-11

525

11-12 Vol. 3

526

11.4 CACHE CONTROL PROTOCOL

527

11.5 CACHE CONTROL

528

Vol. 3 11-15

529

Vol. 3 11-17

531

11-18 Vol. 3

532

Vol. 3 11-19

533

Pentium II Processors

535

Processor Families

536

Processor Families (Contd.)

537

11.5.3 Preventing Caching

538

Vol. 3 11-25

539

11.5.6.1 Adaptive Mode

540

11.5.6.2 Shared Mode

540

11.6 SELF-MODIFYING CODE

541

AND P6 FAMILY PROCESSORS)

541

11.8 EXPLICIT CACHING

542

Vol. 3 11-29

543

11-30 Vol. 3

544

11.11.2.2 Fixed Range MTRRs

548

550

Vol. 3 11-37

551

Vol. 3 11-39

553

Address Support

554

11.11.5 MTRR Initialization

555

11-42 Vol. 3

556

¼ FirstType

557

11-44 Vol. 3

558

Vol. 3 11-45

559

11-46 Vol. 3

560

Vol. 3 11-47

561

11-48 Vol. 3

562

11.12.2 IA32_PAT MSR

563

11.12.4 Programming the PAT

564

Vol. 3 11-51

565

11-52 Vol. 3

566

CHAPTER 12

567

TECHNOLOGY SYSTEM

567

PROGRAMMING

567

Vol. 3 12-3

569

REGISTERS

570

Vol. 3 12-5

571

• System exceptions:

572

12.6 DEBUGGING MMX CODE

572

12-8 Vol. 3

574

CHAPTER 13

575

13-2 Vol. 3

576

Instructions

577

SSE3, EM, MP, and TS

578

• Memory Access Exceptions:

579

• System Exceptions:

580

Vol. 3 13-7

581

13-8 Vol. 3

582

Vol. 3 13-9

583

13-10 Vol. 3

584

13-12 Vol. 3

586

13.6.1 XSAVE Header

587

FXSAVE/FXRSTOR

589

13-16 Vol. 3

590

EXTENDED STATE SUPPORT

591

13-18 Vol. 3

592

Extended State

593

13-20 Vol. 3

594

CHAPTER 14

595

POWER AND THERMAL MANAGEMENT

595

IA32_MPERF (Addr: E7H)

596

IA32_APERF (Addr: E8H)

596

Vol. 3 14-3

597

Processor Operation

599

14-6 Vol. 3

600

EIST Transition Target

600

IDA/Turbo DISENGAGE

600

14-8 Vol. 3

602

MANAGEMENT

603

14-10 Vol. 3

604

Vol. 3 14-11

605

Clock Applied to Processor

605

Stop-Clock Duty Cycle

605

25% Duty Cycle (example only)

605

14.5.2 Thermal Monitor

606

14-14 Vol. 3

608

TM2 Transition Target

608

Thermal Status Log

609

14-16 Vol. 3

610

Vol. 3 14-17

611

Clock Modulation Facilities

612

Vol. 3 14-19

613

14-20 Vol. 3

614

1234581416222324

615

14-22 Vol. 3

616

CHAPTER 15

617

MACHINE-CHECK ARCHITECTURE

617

PROCESSOR

618

15.3 MACHINE-CHECK MSRS

618

15.3.1.1 IA32_MCG_CAP MSR

619

Vol. 3 15-5

621

EIPV—Error IP valid flag

621

RIPV—Restart IP valid flag

621

. . . .

622

Vol. 3 15-7

623

Vol. 3 15-9

625

15-10 Vol. 3

626

15.3.2.3 IA32_MCi_ADDR MSRs

627

15.3.2.4 IA32_MCi_MISC MSRs

628

15.3.2.5 IA32_MCi_CTL2 MSRs

629

15-14 Vol. 3

630

CMCI_EN—Enable/disable CMCI

630

Vol. 3 15-15

631

15-16 Vol. 3

632

Vol. 3 15-17

633

Machine Check Resources

637

15-22 Vol. 3

638

• Log MC errors

639

• Valid (bit 63) = 1

640

• UC (bit 61) = 1

640

• PCC (bit 57) = 0

640

Vol. 3 15-25

641

15-26 Vol. 3

642

Vol. 3 15-27

643

15.9.1 Simple Error Codes

646

15.9.2 Compound Error Codes

647

15-32 Vol. 3

648

Vol. 3 15-33

649

15-34 Vol. 3

650

Vol. 3 15-35

651

15-36 Vol. 3

652

Vol. 3 15-37

653

15.9.4 Multiple MCA Errors

654

Vol. 3 15-39

655

15-40 Vol. 3

656

15.10.2 Pentium

657

Recovery

660

Vol. 3 15-45

661

15-46 Vol. 3

662

CHAPTER 16

669

STAMP COUNTER

669

16-2 Vol. 3

670

Reserved (set to 1)

671

16-4 Vol. 3

672

Vol. 3 16-5

673

16-6 Vol. 3

674

Vol. 3 16-7

675

64 Processors

676

16.3 DEBUG EXCEPTIONS

677

16-10 Vol. 3

678

Vol. 3 16-11

679

16-12 Vol. 3

680

Vol. 3 16-13

681

RECORDING OVERVIEW

682

Vol. 3 16-15

683

16-16 Vol. 3

684

16.4.4 Branch Trace Messages

685

16-18 Vol. 3

686

16.4.8 LBR Stack

687

16.4.9 BTS and DS Save Area

689

16-22 Vol. 3

690

Figure 16-5. DS Save Area

691

16-26 Vol. 3

694

16-28 Vol. 3

696

Vol. 3 16-29

697

16-30 Vol. 3

698

Vol. 3 16-31

699

16-32 Vol. 3

700

16.5.1 LBR Stack

701

16.6.1 LBR Stack

702

Table 16-9. MSR_LBR_SELECT

703

16-36 Vol. 3

704

16.7.1 MSR_DEBUGCTLA MSR

705

Microarchitecture

706

4 and the

707

Processor Family

707

Vol. 3 16-41

709

Duo Processors

710

Core Duo Processor

711

87654321 0

712

16.10.1 DEBUGCTLMSR Register

713

Vol. 3 16-47

715

16-48 Vol. 3

716

16.11.1 Invariant TSC

717

16-50 Vol. 3

718

CHAPTER 17

719

8086 EMULATION

719

17-2 Vol. 3

720

Vol. 3 17-3

721

Vol. 3 17-5

723

17-6 Vol. 3

724

17.2 VIRTUAL-8086 MODE

726

Vol. 3 17-9

727

17-10 Vol. 3

728

Vol. 3 17-11

729

17-12 Vol. 3

730

17-14 Vol. 3

732

17.2.7 Sensitive Instructions

733

17.2.8 Virtual-8086 Mode I/O

733

IN VIRTUAL-8086 MODE

734

Vol. 3 17-17

735

Virtual-8086 Mode

736

17-20 Vol. 3

738

Vol. 3 17-21

739

17-22 Vol. 3

740

Vol. 3 17-23

741

17-24 Vol. 3

742

Vol. 3 17-25

743

17-26 Vol. 3

744

Vol. 3 17-27

745

I/O Map Base

745

Task-State Segment (TSS)

745

I/O Permission Bit Map

745

17-28 Vol. 3

746

Vol. 3 17-29

747

17-30 Vol. 3

748

Vol. 3 17-31

749

CHAPTER 18

751

MIXING 16-BIT AND 32-BIT CODE

751

18-2 Vol. 3

752

Vol. 3 18-3

753

18-4 Vol. 3

754

Vol. 3 18-5

755

Vol. 3 18-7

757

18.4.4 Parameter Translation

758

Vol. 3 18-9

759

CHAPTER 19

761

ARCHITECTURE COMPATIBILITY

761

19-2 Vol. 3

762

THROUGH SOFTWARE

763

19.5 INTEL MMX TECHNOLOGY

763

19-4 Vol. 3

764

Vol. 3 19-5

765

Later IA-32 Processors

766

Vol. 3 19-7

767

19.17.1 PUSH SP

768

19.18 X87 FPU

769

19.18.2 x87 FPU Status Word

770

19.18.3 x87 FPU Control Word

771

19.18.4 x87 FPU Tag Word

771

19.18.5 Data Types

772

Vol. 3 19-13

773

19.18.6.6 FPU Error Signals

774

Vol. 3 19-15

775

19-16 Vol. 3

776

19.18.7.4 FPREM Instruction

777

19-18 Vol. 3

778

Vol. 3 19-19

779

19.18.9 Obsolete Instructions

780

Vol. 3 19-21

781

19.20.1 Intel

782

387 and Intel

782

Initialization

782

Vol. 3 19-23

783

19-24 Vol. 3

784

Vol. 3 19-25

785

19.22.1.2 Global Pages

786

19.22.1.3 Larger Page Sizes

786

19.23 DEBUG FACILITIES

787

19-28 Vol. 3

788

Vol. 3 19-29

789

19.26 INTERRUPTS

790

19.26.3 IDT Limit

791

Family and Pentium Processors

792

4 and Intel Xeon Processors

792

19.28.2 TSS Selector Writes

793

19.29 CACHE MANAGEMENT

794

Vol. 3 19-35

795

19.30 PAGING

796

19.31 STACK OPERATIONS

797

19.31.2 Error Code Pushes

798

Vol. 3 19-39

799

19.33.1 Segment Wraparound

800

Vol. 3 19-41

801

19.35 BUS LOCKING

802

19.36 BUS HOLD

802

Vol. 3 19-43

803

19-44 Vol. 3

804

Vol. 3 19-45

805

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