
Appendix B: POST Code Diagnostic LED Decoder Intel® Server System SR1600UR TPS
Intel order number E45725-010 Revision 1.8
Table 47. Diagnostic LED POST Code Decoder
Multi-use code (This POST Code is used in different contexts)
0xF2h O O O O X X O X
Seen at the start of Memory Reference Code (MRC)
Start of the very early platform initialization code
Very late in POST, it is the signal that the OS has switched to virtual
memory mode
Memory Error Codes (Accompanied by a beep code)
O O O X O X X X
No Usable Memory Error: No memory in the system, or SPD bad so
no memory could be detected
O O O X O X O X
Channel Training Error: DQ/DQS training failed on a channel during
memory channel initialization.
Memory Test Error: memory failed Hardware BIST.
O O O X O O X O
Population Error: RDIMMs and UDIMMs cannot be mixed in the
system
Mismatch Error: more than 2 Quad Ranked DIMMS in a channel.
Memory Reference Code Progress Codes (Not accompanied by a beep code)
Chipset Initialization Phase
Clock Initialization Phase
SPD Data Collection Phase
Memory Map Creation Phase
Early processor initialization where system BSP is selected
Power-on initialization of the host processor (bootstrap processor)
Host processor cache initialization (including AP)
Starting application processor initialization
Initializing a chipset component
Reading configuration data from memory (SPD on DIMM)
Detecting presence of memory
Programming timing parameters in the memory controller
Configuring memory parameters in the memory controller
Optimizing memory controller settings
Initializing memory, such as ECC init
Allocating resources to PCI busses
Hot Plug PCI controller initialization
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