Intel 21555 Manuale Utente Pagina 136
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136 21555 Non-Transparent PCI-to-PCI Bridge User Manual
List of Registers
Table 41. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Translated Base Register
Bit Name R/W Description
5:0 Reserved R Reserved. Returns 0 when read.
31:6 XLAT_BASE R/W
Contains the translated base address for downstream or upstream
transactions whose initiator bus addresses fall into either the
Downstream I/O or Memory 1, or Upstream I/O or Memory 0 Base
Address range.
The number of bits that are used for the translated base is determined by
the setup register corresponding to that base address and also matches
the number of writable bits in the corresponding BAR.
The remaining bits may be written but are ignored when performing
address translation. When an I/O or memory transaction is initiated by the
21555 on the target bus, the original base address is replaced with the
value contained in this register.
Offsets
Downstream I/O or Memory 1
Translated Base
Upstream I/O or Memory 0 Translated
Base
Primary byte 9B:98h A7:A4h
Secondary byte 9B:98h A7:A4h
CSR byte 06F:06Ch 07B:078h
- 21555 Non-Transparent PCI-to 1
- PCI Bridge 1
- Contents 3
- Preface 1 11
- 1.1 Cautions and Notes 12
- 1.2 Data Units 12
- 1.3 Numbering 12
- 1.4 Signal Nomenclature 13
- 1.5 Register Abbreviations 14
- Introduction 2 15
- Intelligent Subsystem 16
- -time resources 17
- 2.2 Architectural Overview 18
- Introduction 19
- 2.3 Special Applications 20
- 2.4 Programming Notes 20
- 2.4.2 Transaction Forwarding 21
- 2.4.3 ROM Access 21
- Signal Descriptions 3 23
- Signal Descriptions 24
- -Bit Extension Signals 26
- Table 1 28
- Signals 30
- 3.5 Miscellaneous Signals 31
- Address Decoding 4 33
- 4.1 CSR Address Decoding 34
- Setup Register 35
- Base Address Register 35
- Base Address 36
- Address Map 36
- Base Offset 36
- A7463-01 37
- A7464-01 37
- A7465-01 39
- Base + Offset 40
- Translated 40
- A7467-01 41
- 4.5 Configuration Accesses 44
- 4.6 21555 Bar Summary 47
- PCI Bus Transactions 5 49
- 5.2 Posted Write Transactions 50
- 5.2.4.2 Fast Back-to-Back 52
- 5.2.4.3 Write-Through 53
- 5.4 Delayed Read Transactions 55
- 5.4.1 Nonprefetchable Reads 56
- 5.4.2 Prefetchable Reads 57
- -prefetchable 58
- -Through Mode 58
- 5.6 Target Terminations 60
- 5.7 Ordering Rules 61
- Initialization Requirements 6 65
- 6.2 Reset Behavior 66
- 6.3 21555 Initialization 68
- 6.3.2 Without Serial Preload 69
- 6.4 Power Management Support 70
- 6.4.2 PME# Support 71
- -Swap Functionality 72
- -Swap Connections 73
- -Swap Insertion and Removal 75
- Clocking 7 77
- A7497-01 78
- 7.3 66 MHz Support 79
- Parallel ROM Interface 8 81
- Parallel ROM Interface 82
- 8.3 PROM Read by CSR Access 84
- A7456-01 85
- 8.4 PROM Write by CSR Access 86
- 8.5 PROM Dword Read 87
- A7472-01 88
- Serial ROM Interface 9 91
- A7478-01 94
- Serial ROM Interface 95
- Arbitration 10 97
- A7492-01 99
- 11.2 Interrupt Support 101
- 11.3 Doorbell Interrupts 103
- 11.4 Scratchpad Registers 103
- Error Handling 12 105
- Error Handling 106
- 12.2 Parity Errors 107
- JTAG Test Port 13 111
- 13.2.1 Initialization 112
- I2O Support 14 113
- 14.2 Outbound Message Passing 115
- 14.3 Notes 116
- VPD Support 15 119
- 15.2 Writing VPD Information 120
- List of Registers 16 121
- 16.2 Configuration Registers 122
- List of Registers 123
- 16.4 Address Decoding 130
- (Sheet 1 of 2) 131
- (Sheet 2 of 2) 131
- (Sheet 2 of 2) 132
- -only bit and always 133
- -bit memory 134
- -bit addressing and 134
- Bit Name R/W Description 140
- -Response 143
- Table 53. I/O CSR 146
- 16.5 PCI Registers 147
- Table 59. Vendor ID Register 148
- Table 60. Device ID Register 148
- -Class Code (SCC) 152
- Table 68. BiST Register 153
- -MHz bus 157
- -robin arbitration scheme to 157
- 16.6 I2O Registers 165
- Table 85. I2O Inbound Queue 166
- Table 86. I2O Outbound Queue 166
- 16.7 Interrupt Registers 170
- 16.8 Scratchpad Registers 174
- 16.9 PROM Registers 175
- Table 109. ROM Setup Register 177
- Table 110. ROM Data Register 177
- 16.10 SROM Registers 179
- -Class Code 181
- 16.11 Arbiter Control 183
- 16.12 Error Registers 183
- -out condition 184
- 16.13 Init Registers 185
- -Swap registers 189
- JTAG Registers 190
- 16.15 VPD Registers 192
- -byte operations 193
- Acronyms A 195
- VGA – Video Graphics Adapter 196
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