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Intel® 41210 Serial to Parallel PCI Bridge Design Guide 39

PCI-X Layout Guidelines

8.6.1 Embedded PCI-X 133 MHz

This section lists the routing recommendations for PCI-X 133 MHz without a slot. Figure 18 shows

the block diagram of this topology and Table 10 describes the routing recommendations.

Figure 18. Embedded PCI-X 133 MHz Topology

Table 10. Embedded PCI-X 133 MHz Routing Recommendations

Parameter Routing Guideline for Lower AD Bus

Reference Plane Route over an unbroken ground plane

Board Impedance 60 Ω +/- 15%

Stripline Trace Spacing 12 mils from edge to edge

Microstrip Trace Spacing 18 mils, from edge to edge

Break Out 5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils

Group Spacing Spacing from other groups: 25 mils min, edge to edge

Trace Length 1 (TL1): From

41210 Bridge signal Ball to

first junction

1.75” min - 4.0” max

Trace Length 3 junction of

TL_EM1 and TL_EM2 to the

embedded device

1.25” min - 3.25” max

Length Matching

Requirements:

Clocks coming form the clock driver must be on the same layer and length

matched to within 25 mils.

Number of vias 3 vias max per path

B2719 -01

EM1

EM2

TL1

TL_EM2 TL_EM1

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Intel 41210 Manuale Utente Pagina 39