Intel AT80571PG0642ML Scheda Tecnica

Document Number: 320467-005Intel® Pentium® Dual-Core Processor E6000Δ and E5000Δ SeriesDatasheetAugust 2009

Introduction10 Datasheet“Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB

Debug Tools Specifications100 Datasheet

Datasheet 11Introductionsecurity of the system. See the Intel® Architecture Software Developer's Manual for more detailed information.• Intel® 64

Introduction12 Datasheet

Datasheet 13Electrical Specifications2 Electrical SpecificationsThis chapter describes the electrical characteristics of the processor interfaces and

Electrical Specifications14 Datasheet2.2.3 FSB DecouplingThe processor integrates signal termination on the die. In addition, some of the high frequen

Datasheet 15Electrical SpecificationsTable 2. Voltage Identification DefinitionVID7VID6VID5VID4VID3VID2VID1VID0VoltageVID7VID6VID5VID4VID3VID2VID1VID0

Electrical Specifications16 Datasheet2.4 Reserved, Unused, and TESTHI SignalsAll RESERVED lands must remain unconnected. Connection of these lands to

Datasheet 17Electrical Specifications2.6 Voltage and Current Specification2.6.1 Absolute Maximum and Minimum RatingsTa b le 3 specifies absolute maxi

Electrical Specifications18 Datasheet2.6.2 DC Voltage and Current SpecificationNOTES:1. Each processor is programmed with a maximum valid voltage iden

Datasheet 19Electrical Specificationsprobe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

2 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO A

Electrical Specifications20 DatasheetNOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as sho

Datasheet 21Electrical SpecificationsNOTES:1. VOS is measured overshoot voltage.2. TOS is measured time duration above VID.2.6.4 Die Voltage Validatio

Electrical Specifications22 Datasheet2.7.1 FSB Signal GroupsThe front side bus signals have been combined into groups by buffer type. GTL+ input signa

Datasheet 23Electrical Specifications3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration op

Electrical Specifications24 Datasheet2.7.3 Processor DC SpecificationsThe processor DC specifications in this section are defined at the processor cor

Datasheet 25Electrical SpecificationsNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. All outpu

Electrical Specifications26 Datasheet.2.7.3.2 GTL+ Front Side Bus SpecificationsIn most cases, termination resistors are not required as these are int

Datasheet 27Electrical SpecificationsNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. GTLREF is

Electrical Specifications28 DatasheetNOTES:1. Individual processors operate only at or below the rated frequency. 2. Listed frequencies are not necess

Datasheet 29Electrical Specifications2.8.3 Phase Lock Loop (PLL) and FilterAn on-die PLL filter solution will be implemented on the processor. The VCC

Datasheet 3Contents1Introduction...91.1 Ter

Electrical Specifications30 DatasheetNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies based o

Datasheet 31Electrical Specifications§ §Figure 3. Differential Clock WaveformThresholdRegionVHVLOvershootUndershootRingbackMargin Rising EdgeRingback

Electrical Specifications32 Datasheet

Datasheet 33Package Mechanical Specifications3 Package Mechanical SpecificationsThe processor is packaged in a Flip-Chip Land Grid Array (FC-LGA8) pac

Package Mechanical Specifications34 DatasheetFigure 6. Processor Package Drawing Sheet 1 of 3

Datasheet 35Package Mechanical SpecificationsFigure 7. Processor Package Drawing Sheet 2 of 3

Package Mechanical Specifications36 DatasheetFigure 8. Processor Package Drawing Sheet 3 of 3

Datasheet 37Package Mechanical Specifications3.2 Processor Component Keep-Out ZonesThe processor may contain components on the substrate that define c

Package Mechanical Specifications38 Datasheet3.5 Package Insertion SpecificationsThe processor can be inserted into and removed from a LGA775 socket 1

Datasheet 39Package Mechanical SpecificationsFigure 10. Intel® Pentium® Dual-Core Processor E6000 Series Top-Side Markings ExampleATPOS/NINTEL ©&apos

4 Datasheet5.3.1 Introduction...825.3.1.1 TCONTROL and TCC act

Package Mechanical Specifications40 Datasheet3.9 Processor Land CoordinatesFigure 11 shows the top view of the processor land coordinates. The coordin

Datasheet 41Land Listing and Signal Descriptions4 Land Listing and Signal DescriptionsThis chapter provides the processor land assignment and signal d

Land Listing and Signal Descriptions42 DatasheetFigure 12. land-out Diagram (Top View – Left Side)30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15ANVCC

Datasheet 43Land Listing and Signal DescriptionsFigure 13. land-out Diagram (Top View – Right Side)14 13 12 11 10 9 8 7 6 5 4 3 2 1VCC VSS VCC VCC VSS

Land Listing and Signal Descriptions44 DatasheetTable 23. Alphabetical Land AssignmentsLand NameLand #Signal Buffer TypeDirectionA3# L5 Source Synch I

Land Listing and Signal DescriptionsDatasheet 45D22# D10 Source Synch Input/OutputD23# F11 Source Synch Input/OutputD24# F12 Source Synch Input/Output

Land Listing and Signal Descriptions46 DatasheetFC31 J16 Power/OtherFC32 H15 Power/OtherFC33 H16 Power/OtherFC34 J17 Power/OtherFC35 H4 Power/OtherFC3

Land Listing and Signal DescriptionsDatasheet 47TRDY# E3 Common Clock InputTRST# AG1 TAP InputVCC AA8 Power/Other VCC AB8 Power/Other VCC AC23 Power

Land Listing and Signal Descriptions48 DatasheetVCC AJ18 Power/Other VCC AJ19 Power/Other VCC AJ21 Power/Other VCC AJ22 Power/Other VCC AJ25 Power

Land Listing and Signal DescriptionsDatasheet 49VCC J28 Power/Other VCC J29 Power/Other VCC J30 Power/Other VCC J8 Power/Other VCC J9 Power/Other

Datasheet 5Figures1 Processor VCC Static and Transient Tolerance... 202VCC Overshoot Examp

Land Listing and Signal Descriptions50 DatasheetVID0 AM2 Asynch CMOS OutputVID1 AL5 Asynch CMOS OutputVID2 AM3 Asynch CMOS OutputVID3 AL6 Asynch CMOS

Land Listing and Signal DescriptionsDatasheet 51VSS AF30 Power/Other VSS AF6 Power/Other VSS AF7 Power/Other VSS AG10 Power/Other VSS AG13 Power/O

Land Listing and Signal Descriptions52 DatasheetVSS AN24 Power/Other VSS AN27 Power/Other VSS AN28 Power/Other VSS C10 Power/Other VSS C13 Power/O

Land Listing and Signal DescriptionsDatasheet 53VSS N6 Power/Other VSS N7 Power/Other VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other

Land Listing and Signal Descriptions54 DatasheetTable 24. Numerical Land AssignmentLand # Land NameSignal Buffer TypeDirectionA2 VSS Power/Other A3 R

Land Listing and Signal DescriptionsDatasheet 55C20 DBI3# Source Synch Input/OutputC21 D58# Source Synch Input/OutputC22 VSS Power/Other C23 VCCIOPLL

Land Listing and Signal Descriptions56 DatasheetF11 D23# Source Synch Input/OutputF12 D24# Source Synch Input/OutputF13 VSS Power/Other F14 D28# Sour

Land Listing and Signal DescriptionsDatasheet 57H29 FC15 Power/Other H30 BSEL1 Asynch CMOS OutputJ1VTT_OUT_LEFTPower/Other OutputJ2 FC3 Power/OtherJ3

Land Listing and Signal Descriptions58 DatasheetM29 VCC Power/Other M30 VCC Power/Other N1 PWRGOOD Power/Other InputN2 IGNNE# Asynch CMOS InputN3 VS

Land Listing and Signal DescriptionsDatasheet 59U27 VCC Power/Other U28 VCC Power/Other U29 VCC Power/Other U30 VCC Power/Other V1 MSID1 Power/Oth

6 DatasheetTables1 References ...112 Voltag

Land Listing and Signal Descriptions60 DatasheetAB24 VSS Power/Other AB25 VSS Power/Other AB26 VSS Power/Other AB27 VSS Power/Other AB28 VSS Power

Land Listing and Signal DescriptionsDatasheet 61AF10 VSS Power/Other AF11 VCC Power/Other AF12 VCC Power/Other AF13 VSS Power/Other AF14 VCC Power

Land Listing and Signal Descriptions62 DatasheetAH28 VCC Power/Other AH29 VCC Power/Other AH30 VCC Power/Other AJ1 BPM1# Common Clock Input/OutputA

Land Listing and Signal DescriptionsDatasheet 63AL16 VSS Power/Other AL17 VSS Power/Other AL18 VCC Power/Other AL19 VCC Power/Other AL20 VSS Power

Land Listing and Signal Descriptions64 Datasheet4.2 Alphabetical Signals ReferenceTable 25. Signal Description (Sheet 1 of 10)Name Type DescriptionA[

Datasheet 65Land Listing and Signal DescriptionsBPM[5:0]#Input/OutputBPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. Th

Land Listing and Signal Descriptions66 DatasheetD[63:0]#Input/OutputD[63:0]# (Data) are the data signals. These signals provide a 64-bit data path bet

Datasheet 67Land Listing and Signal DescriptionsDEFER# InputDEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order c

Land Listing and Signal Descriptions68 DatasheetFERR#/PBE# OutputFERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its

Datasheet 69Land Listing and Signal DescriptionsITP_CLK[1:0] InputITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no deb

Datasheet 7Intel® Pentium® Dual-Core Processor E6000 and E5000 Series FeaturesThe Intel® Pentium® dual-core processor E6000 and E5000 series is based

Land Listing and Signal Descriptions70 DatasheetPWRGOOD InputPWRGOOD (Power Good) is a processor input. The processor requires this signal to be a cle

Datasheet 71Land Listing and Signal DescriptionsSLP# InputSLP# (Sleep), when asserted in Extended Stop Grant or Stop Grant state, causes the processor

Land Listing and Signal Descriptions72 DatasheetTHERMTRIP# OutputIn the event of a catastrophic cooling failure, the processor will automatically shut

Land Listing and Signal Descriptions73 DatasheetVID[7:0] OutputThe VID (Voltage ID) signals are used to support automatic selection of power supply vo

Land Listing and Signal Descriptions74 Datasheet

Datasheet 75Thermal Specifications and Design Considerations5 Thermal Specifications and Design Considerations5.1 Processor Thermal SpecificationsThe

Thermal Specifications and Design Considerations76 DatasheetThe case temperature is defined at the geometric top center of the processor. Analysis ind

Datasheet 77Thermal Specifications and Design ConsiderationsTable 27. Processor Thermal ProfilePower (W)Maximum Tc (°C)PowerMaximum Tc (°C)PowerMaximu

Thermal Specifications and Design Considerations78 Datasheet5.1.2 Thermal MetrologyThe maximum and minimum case temperatures (TC) for the processor is

Datasheet 79Thermal Specifications and Design Considerationsperiods of TCC activation is expected to be so minor that it would be immeasurable. An und

8 DatasheetRevision History§ §Revision NumberDescription Revision Date-001 • Initial releaseAugust 2008-002•Intel® Pentium® dual-core processor E5300

Thermal Specifications and Design Considerations80 DatasheetThe PROCHOT# signal is asserted when a high temperature situation is detected, regardless

Datasheet 81Thermal Specifications and Design Considerations5.2.4 PROCHOT# SignalAn external signal, PROCHOT# (processor hot), is asserted when the pr

Thermal Specifications and Design Considerations82 Datasheet5.3 Platform Environment Control Interface (PECI)5.3.1 IntroductionPECI offers an interfac

Datasheet 83Thermal Specifications and Design Considerations5.3.2 PECI Specifications5.3.2.1 PECI Device AddressThe PECI register resides at address 3

Thermal Specifications and Design Considerations84 Datasheet

Datasheet 85Features6 Features6.1 Power-On Configuration OptionsSeveral configuration options can be configured by hardware. The processor samples the

Features86 Datasheet6.2.1 Normal StateThis is the normal operating state for the processor.6.2.2 HALT and Extended HALT Powerdown StatesThe processor

Datasheet 87FeaturesThe return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT powerdown state. See the Inte

Features88 Datasheet6.2.3.2 Extended Stop Grant State Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted and Extende

Datasheet 89Featuresbehavior.If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin spec

Datasheet 9Introduction1 IntroductionThe Intel® Pentium® dual-core processor E6000 and E5000 series are based on the Enhanced Intel® Core™ microarchit

Features90 DatasheetIn response to entering Deeper Sleep, the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID

Datasheet 91Boxed Processor Specifications7 Boxed Processor Specifications7.1 IntroductionThe processor will also be offered as an Intel boxed process

Boxed Processor Specifications92 Datasheet7.2 Mechanical Specifications7.2.1 Boxed Processor Cooling Solution DimensionsThis section documents the mec

Datasheet 93Boxed Processor Specifications7.2.2 Boxed Processor Fan Heatsink WeightThe boxed processor fan heatsink will not weigh more than 450 grams

Boxed Processor Specifications94 DatasheetThe boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and does not support var

Datasheet 95Boxed Processor Specifications7.4 Thermal SpecificationsThis section describes the cooling requirements of the fan heatsink solution used

Boxed Processor Specifications96 Datasheet Figure 25. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)Figure 26. Boxed Process

Datasheet 97Boxed Processor Specifications7.4.2 Variable Speed FanIf the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherbo

Boxed Processor Specifications98 DatasheetIf the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the mothe

Datasheet 99Debug Tools Specifications8 Debug Tools Specifications8.1 Logic Analyzer Interface (LAI)Intel is working with two logic analyzer vendors t