Intel CP80617004803AA Scheda Tecnica

Document Number: 324471-001Intel® Celeron® Mobile Processor P4000 and U3000 SeriesDatasheetRevision 001October 2010

Features Summary10 DatasheetFigure 1-1.Intel® Celeron® P4000 and U3000 mobile processor series on the Calpella PlatformProcessor Discrete Graphics (PE

Electrical Specifications100 DatasheetNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. VIL is d

Datasheet 101Electrical SpecificationsNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. The VTT

Electrical Specifications102 DatasheetNOTES:1. Refer to the PCI Express Base Specification for more details.2. VTX-AC-CM-PP and VTX-AC-CM-P are define

Datasheet 103Electrical SpecificationsNOTES:1. VAUX-DIFFp-p = 2*|VAUXP  VAUXM|. Please refer to the VESA DisplayPort Standard specification for more

Electrical Specifications104 DatasheetNOTES:1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications.2. The leakag

Datasheet 105Processor Pin and Signal Information8 Processor Pin and Signal Information8.1 Processor Pin Assignments Provides a listing of all proces

Processor Pin and Signal Information106 DatasheetFigure 8-17.Socket-G (rPGA988A) Pinmap (Top View, Upper-Left Quadrant)VTT0SB_CK# [0]SB_CK[0] VDDQVSSS

Datasheet 107Processor Pin and Signal InformationFigure 8-18.Socket-G (rPGA988A) Pinmap (Top View, Upper-Right Quadrant)2 3 2 2 2 1 2 0 19 18 17 16 15

Processor Pin and Signal Information108 DatasheetFigure 8-19.Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant)U V CC VCC V CC VCC VCC VCC VCC

Datasheet 109Processor Pin and Signal InformationFigure 8-20.Socket-G (rPGA988A) Pinmap (Top View, Lower-Right Quadrant)VTT0 RSVD VSSSA_BS[2]SA_MA[9]S

Datasheet 11Features Summary1.2 Processor Feature Details Two execution cores A 32-KB instruction and 32-KB data first-level cache (L1) for each cor

Datasheet 110Processor Pin and Signal InformationTable 8-48.rPGA988A Processor Pin List by Pin NumberPin NumberPin NameBuffer TypeDir.A2 KEYA3 RSVD_NC

111 DatasheetProcessor Pin and Signal InformationAB30 VSS GNDAB31 VSS GNDAB32 VSS GNDAB33 VSS GNDAB34 VSS GNDAB35 VSS GNDAC1 VDDQ REFAC2 VSS GNDAC3 SA

Datasheet 112Processor Pin and Signal InformationAF7 SB_MA[13] DDR3 OAF8 VSS GNDAF9 SA_ODT[1] DDR3 OAF10 VTT0 REFAF26 VCC REFAF27 VCC REFAF28 VCC REFA

113 DatasheetProcessor Pin and Signal InformationAJ4 SB_DQ[38] DDR3 I/OAJ5 VSS GNDAJ6 SA_DQ[39] DDR3 I/OAJ7 SA_DQ[38] DDR3 I/OAJ8 VSS GNDAJ9 SA_DQ[41]

114 DatasheetProcessor Pin and Signal InformationAL5 SB_DQS[5] DDR3 I/OAL6 VSS GNDAL7 SA_DQ[45] DDR3 I/OAL8 SA_DQ[47] DDR3 I/OAL9 VSS GNDAL10 SA_DQ[42

Datasheet 115Processor Pin and Signal InformationAN5 SB_DQ[49] DDR3 I/OAN6 SB_DQ[51] DDR3 I/OAN7 SB_DQ[56] DDR3 I/OAN8 SA_DQ[48] DDR3 I/OAN9 SA_DQ[53]

116 DatasheetProcessor Pin and Signal InformationAR1 RSVD_NCTFAR2 RSVD_NCTFAR3 VSS GNDAR4 SB_DM[6] DDR3 OAR5 SB_DQS#[6] DDR3 I/OAR6 VSS GNDAR7 SB_DQS[

Datasheet 117Processor Pin and Signal InformationB1 VSS_NCTFB2 VSS_NCTFB3 SB_DQ[3] DDR3 I/OB4 VSS GNDB5 SB_DQ[0] DDR3 I/OB6 VSS GNDB7 SA_DQ[13] DDR3 I

118 DatasheetProcessor Pin and Signal InformationD3 VSS GNDD4 SB_DM[0] DDR3 OD5 SB_DQS#[0] DDR3 I/OD6 VSS GNDD7 SA_DM[1] DDR3 OD8 SA_DQ[8] DDR3 I/OD9

119 DatasheetProcessor Pin and Signal InformationF5 SB_DQ[13] DDR3 I/OF6 SM_DRAMRST# DDR3 OF7 SA_DQ[11] DDR3 I/OF8 SA_DQS#[1] DDR3 I/OF9 SA_DQS[1] DDR

Features Summary12 DatasheetDual-channel symmetric (Interleaved)Dual-channel asymmetric Command launch modes of 1n/2n Partial Writes to memory using

Datasheet 120Processor Pin and Signal InformationH7 SA_DM[2] DDR3 OH8 VSS GNDH9 SA_DQS[2] DDR3 I/OH10 SA_DQ[16] DDR3 I/OH11 VSS GNDH12 VTT0 REFH13 VSS

121 DatasheetProcessor Pin and Signal InformationK9 VSS GNDK10 VTT0 REFK26 VTT1 REFK27 VSS GNDK28 PEG_TX[8] PCIe OK29 PEG_TX#[8] PCIe OK30 VSS GNDK31

Datasheet 122Processor Pin and Signal InformationP1 VDDQ REFP2 VSS GNDP3 SB_MA[11] DDR3 OP4 VSS GNDP5 SB_MA[14] DDR3 OP6 SA_CKE[1] DDR3 OP7 SA_CKE[0]

123 DatasheetProcessor Pin and Signal InformationU28 VCC REFU29 VCC REFU30 VCC REFU31 VCC REFU32 VCC REFU33 VCC REFU34 VCC REFU35 VCC REFV1 SA_MA[4] D

Datasheet 124Processor Pin and Signal InformationTable 8-49.rPGA988A Processor Pin List by Pin NamePin NamePin NumberBuffer TypeDir.BCLK A16 DIFF CLK

125 DatasheetProcessor Pin and Signal InformationFDI_TX#[4] G21 FDI OFDI_TX#[5] E19 FDI OFDI_TX#[6] F21 FDI OFDI_TX#[7] G18 FDI OGFX_DPRSLPVR AT25 CMO

Datasheet 126Processor Pin and Signal InformationPEG_TX#[1] M35 PCIe OPEG_TX#[2] M33 PCIe OPEG_TX#[3] M30 PCIe OPEG_TX#[4] L31 PCIe OPEG_TX#[5] K32 PC

127 DatasheetProcessor Pin and Signal InformationRSVD_NCTF A34RSVD_NCTF AP1RSVD_NCTF AP35RSVD_NCTF AR1RSVD_NCTF AR2RSVD_NCTF AR35RSVD_NCTF AT3RSVD_NCT

Datasheet 128Processor Pin and Signal InformationSA_DQ[12] E9 DDR3 I/OSA_DQ[13] B7 DDR3 I/OSA_DQ[14] E7 DDR3 I/OSA_DQ[15] C6 DDR3 I/OSA_DQ[16] H10 DDR

129 DatasheetProcessor Pin and Signal InformationSA_MA[4] V1 DDR3 OSA_MA[5] AA9 DDR3 OSA_MA[6] V8 DDR3 OSA_MA[7] T1 DDR3 OSA_MA[8] Y9 DDR3 OSA_MA[9] U

Datasheet 13Features Summarynon-zero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped. Re-

Datasheet 130Processor Pin and Signal InformationSB_DQ[36] AG4 DDR3 I/OSB_DQ[37] AG3 DDR3 I/OSB_DQ[38] AJ4 DDR3 I/OSB_DQ[39] AH4 DDR3 I/OSB_DQ[40] AK3

131 DatasheetProcessor Pin and Signal InformationTCK AN28 CMOS ITDI AT29 CMOS ITDI_M AR29 CMOS ITDO AR27 CMOS OTDO_M AP29 CMOS OTHERMTRIP# AK15 Async

Datasheet 132Processor Pin and Signal InformationVCC AD33 REFVCC AD34 REFVCC AD35 REFVCC AF26 REFVCC AF27 REFVCC AF28 REFVCC AF29 REFVCC AF30 REFVCC A

133 DatasheetProcessor Pin and Signal InformationVCC Y35 REFVCC_SENSE AJ34 Analog OVCCPLL L26 REFVCCPLL L27 REFVCCPLL M26 REFVCCPWRGOOD_0AN27 Async CM

Datasheet 134Processor Pin and Signal InformationVSS AH27 GNDVSS AH28 GNDVSS AH29 GNDVSS AH3 GNDVSS AH30 GNDVSS AH31 GNDVSS AH32 GNDVSS AH33 GNDVSS AH

135 DatasheetProcessor Pin and Signal InformationVSS B11 GNDVSS B13 GNDVSS B17 GNDVSS B18 GNDVSS B21 GNDVSS B25 GNDVSS B31 GNDVSS B4 GNDVSS B6 GNDVSS

Datasheet 136Processor Pin and Signal InformationVSS L2 GNDVSS L29 GNDVSS L32 GNDVSS L35 GNDVSS L5 GNDVSS L8 GNDVSS M10 GNDVSS N26 GNDVSS N27 GNDVSS N

137 DatasheetProcessor Pin and Signal InformationVTT0 AH11 REFVTT0 AH12 REFVTT0 AH14 REFVTT0 B12 REFVTT0 B14 REFVTT0 C11 REFVTT0 C12 REFVTT0 C13 REFVT

Datasheet 138Processor Pin and Signal InformationFigure 8-21.BGA1288 Ballmap (Top View, Upper-Left Quadrant)

139 DatasheetProcessor Pin and Signal InformationFigure 8-22.BGA1288 Ballmap (Top View, Upper-Right Quadrant)

Features Summary14 Datasheet Processor core -> DMI APIC and MSI interrupt messaging support: Message Signaled Interrupt (MSI and MSI-X) messages

Datasheet 140Processor Pin and Signal InformationFigure 8-23.BGA1288 Ballmap (Top View, Lower-Left Quadrant)

141 DatasheetProcessor Pin and Signal InformationFigure 8-24.BGA1288 Ballmap (Top View, Lower-Right Quadrant)

Datasheet 142Processor Pin and Signal InformationTable 8-50.BGA1288 Processor Ball List by Ball Name (Sheet 1 of 37)Pin Name Pin #Buffer TypeDirBCLKA

143 DatasheetProcessor Pin and Signal InformationDMI_TX[3] J11 DMI ODMI_TX#[0] H17 DMI ODMI_TX#[1] K15 DMI ODMI_TX#[2] J13 DMI ODMI_TX#[3] F10 DMI ODP

Datasheet 144Processor Pin and Signal InformationPEG_RX#[7] D29 PCIe IPEG_RX#[8] B26 PCIe IPEG_RX#[9] D26 PCIe IPEG_RX#[10] B23 PCIe IPEG_RX#[11] D22

145 DatasheetProcessor Pin and Signal InformationRSVD AP66RSVD AR69RSVD AR71RSVD AT67RSVD AT70RSVD AU2RSVD AU69RSVD AU71RSVD AV4RSVD AV69RSVD AV71RSVD

Datasheet 146Processor Pin and Signal InformationSA_DQ[19] BK15 DDR3 I/OSA_DQ[20] BK9 DDR3 I/OSA_DQ[21] BG15 DDR3 I/OSA_DQ[22] BH17 DDR3 I/OSA_DQ[23]

147 DatasheetProcessor Pin and Signal InformationSA_MA[11] BH30 DDR3 OSA_MA[12] BJ28 DDR3 OSA_MA[13] BF40 DDR3 OSA_MA[14] BN28 DDR3 OSA_MA[15] BN25 DD

Datasheet 148Processor Pin and Signal InformationSB_DQ[43] BT57 DDR3 I/OSB_DQ[44] BP56 DDR3 I/OSB_DQ[45] BT55 DDR3 I/OSB_DQ[46] BU60 DDR3 I/OSB_DQ[47]

149 DatasheetProcessor Pin and Signal InformationTRST# P69 CMOS IVAXG AD17 REFVAXG AD19 REFVAXG AD21 REFVAXG AD23 REFVAXG AD24 REFVAXG AD26 REFVAXG AD

Datasheet 15Features Summary1.3.6 Embedded DisplayPort* (eDP*) Shared with PCI Express Graphics port Shared on upper four logical lanes, after any l

Datasheet 150Processor Pin and Signal InformationVCAP1 AN39 PWRVCAP1 AN42 PWRVCAP1 AN46 PWRVCAP1 AR37 PWRVCAP1 AR41 PWRVCAP1 AR44 PWRVCAP1 AU37 PWRVCA

151 DatasheetProcessor Pin and Signal InformationVCC B49 REFVCC B53 REFVCC B56 REFVCC B60 REFVCC D43 REFVCC D45 REFVCC D47 REFVCC D48 REFVCC D50 REFVC

Datasheet 152Processor Pin and Signal InformationVDDQ BB24 REFVDDQ BB26 REFVDDQ BB28 REFVDDQ BB30 REFVDDQ BB32 REFVDDQ BB33 REFVDDQ BB35 REFVDDQ BD15

153 DatasheetProcessor Pin and Signal InformationVSS AA4 GNDVSS AA42 GNDVSS AA46 GNDVSS AA50 GNDVSS AA53 GNDVSS AA57 GNDVSS AA62 GNDVSS AA64 GNDVSS AA

Datasheet 154Processor Pin and Signal InformationVSS AH50 GNDVSS AH51 GNDVSS AH53 GNDVSS AH55 GNDVSS AH57 GNDVSS AH62 GNDVSS AJ70 GNDVSS AK15 GNDVSS A

155 DatasheetProcessor Pin and Signal InformationVSS AU14 GNDVSS AU15 GNDVSS AU17 GNDVSS AU19 GNDVSS AU21 GNDVSS AU23 GNDVSS AU24 GNDVSS AU26 GNDVSS A

Datasheet 156Processor Pin and Signal InformationVSS BB50 GNDVSS BB53 GNDVSS BB57 GNDVSS BB62 GNDVSS BB7 GNDVSS BB71 GNDVSS BD14 GNDVSS BD39 GNDVSS BD

157 DatasheetProcessor Pin and Signal InformationVSS BU55 GNDVSS BU58 GNDVSS BU62 GNDVSS BU7 GNDVSS BV64 GNDVSS BV66 GNDVSS C68 GNDVSS D10 GNDVSS D13

Datasheet 158Processor Pin and Signal InformationVSS M42 GNDVSS M53 GNDVSS N15 GNDVSS N21 GNDVSS N30 GNDVSS N46 GNDVSS N50 GNDVSS N53 GNDVSS N57 GNDVS

159 DatasheetProcessor Pin and Signal InformationVTT0 AN35 REFVTT0 AN59 REFVTT0 AN60 REFVTT0 AN9 REFVTT0 AR12 REFVTT0 AR59 REFVTT0 AR60 REFVTT0 AU12 R

Features Summary16 Datasheet1.4.3 Memory Controller Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM)) Dynamic power-down

Datasheet 160Processor Pin and Signal InformationVTT1 W12 REFVTT1 W14 REFVTT1 W15 REFVTT1 W17 REFVTT1 W19 REFVTT1 W21 REFVTTPWRGOOD H15 Async CMOSITab

161 DatasheetProcessor Pin and Signal InformationAA42 VSS GNDAA44 VCC REFAA46 VSS GNDAA48 VCC REFAA50 VSS GNDAA51 VCC REFAA53 VSS GNDAA55 VCC REFAA57

Datasheet 162Processor Pin and Signal InformationAD26 VAXG REFAD28 VAXG REFAD30 VTT0 REFAD32 VTT0 REFAD33 VTT0 REFAD35 VTT0 REFAD37 VTT0 REFAD39 VTT0

163 DatasheetProcessor Pin and Signal InformationAH12 VAXG REFAH14 VAXG REFAH15 VSS GNDAH17 VSS GNDAH19 VSS GNDAH21 VSS GNDAH23 VSS GNDAH24 VSS GNDAH2

Datasheet 164Processor Pin and Signal InformationAK66 RSVDAK69 RSVDAK70 VSS GNDAK71 RSVDAL1 VSS GNDAL4 CFG[0] CMOS IAL12 VTT0 REFAL14 VTT0 REFAL15 VTT

165 DatasheetProcessor Pin and Signal InformationAN46 VCAP1 PWRAN48 VSS GNDAN50 VCAP0 PWRAN51 VSS GNDAN53 VCAP0 PWRAN55 VSS GNDAN57 VCAP0 PWRAN59 VTT0

Datasheet 166Processor Pin and Signal InformationAU35 VSS GNDAU37 VCAP1 PWRAU39 VSS GNDAU41 VCAP1 PWRAU42 VSS GNDAU44 VCAP1 PWRAU46 VSS GNDAU48 VCAP0

167 DatasheetProcessor Pin and Signal InformationAY23 VSS GNDAY24 VSS GNDAY26 VSS GNDAY28 VSS GNDAY30 VSS GNDAY32 VSS GNDAY33 VSS GNDAY35 VSS GNDAY37

Datasheet 168Processor Pin and Signal InformationBB17 VDDQ REFBB19 VDDQ REFBB21 VDDQ REFBB23 VDDQ REFBB24 VDDQ REFBB26 VDDQ REFBB28 VDDQ REFBB30 VDDQ

169 DatasheetProcessor Pin and Signal InformationBE64 SA_DQS[7] DDR3 I/OBE65 VSS GNDBE69 RSVDBE70 VSS GNDBE71 RSVDBF2 SB_DQ[6] DDR3 I/OBF6 SA_DQ[13] D

Datasheet 17Features Summary1.7 TerminologyTerm DescriptionBLT Block Level TransferCRT Cathode Ray TubeDDR3 Third-generation Double Data Rate SDRAM me

Datasheet 170Processor Pin and Signal InformationBJ1 VSS GNDBJ4 SB_DQ[12] DDR3 I/OBJ5 SA_DQS[1] DDR3 I/OBJ7 SA_DQS#[1] DDR3 I/OBJ9 VSS GNDBJ10 SA_DM[1

171 DatasheetProcessor Pin and Signal InformationBM70 VSS GNDBN1 VSS GNDBN4 SB_DQS[1] DDR3 I/OBN6 VSS GNDBN8 SA_DQ[15] DDR3 I/OBN9 SA_DQ[17] DDR3 I/OB

Datasheet 172Processor Pin and Signal InformationBT33 SB_MA[5] DDR3 OBT34 SB_MA[0] DDR3 OBT36 SA_MA[0] DDR3 OBT38 SA_BS[0] DDR3 OBT40 SB_RAS# DDR3 OBT

173 DatasheetProcessor Pin and Signal InformationBV33 SM_RCOMP[0] Analog IBV34 SB_CK#[0] DDR3 OBV36 SA_MA[2] DDR3 OBV38 SB_CK[1] DDR3 OBV40 SM_RCOMP[2

Datasheet 174Processor Pin and Signal InformationE46 VCC REFE50 VCC REFE53 VCC REFE57 VCC REFE60 VCC REFE68 VSS GNDE69 VSS GNDE71 DC_TEST_E71F1 RSVD_N

175 DatasheetProcessor Pin and Signal InformationJ9 VSS GNDJ20 PEG_TX#[15] PCIe OJ21 PEG_CLK# DIFF CLKIJ28 PEG_RX[4] PCIe IJ30 PEG_TX[8] PCIe OJ38 PEG

Datasheet 176Processor Pin and Signal InformationM71 PROC_DETECTN2 FDI_TX[2] FDI ON5 FDI_TX[1] FDI ON7 FDI_TX#[1] FDI ON9 FDI_TX[4] FDI ON10 FDI_TX#[4

177 DatasheetProcessor Pin and Signal InformationR60 VCAP2 PWRR62 VSS GNDR64 RSVDR66 RSVDR70 VSS GNDT1 VSS GNDT2 RSVDT4 RSVDU6 FDI_TX[6] FDI OU7 FDI_T

Processor Pin and Signal Information178 DatasheetW37 VCCPLL REFW39 VCCPLL REFW41 VCC REFW42 VSS GNDW44 VCC REFW46 VSS GNDW48 VCC REFW50 VSS GNDW51 VCC

Datasheet 179Processor Pin and Signal Information8.2 Package Mechanical InformationFigure 8-25. rPGA Mechanical Package (Sheet 1 of 2)

Features Summary18 DatasheetPCH Platform Controller Hub. The new, 2009 chipset with centralized platform capabilities including the main I/O interface

Processor Pin and Signal Information180 DatasheetFigure 8-26.rPGA Mechanical Package (Sheet 2 of 2)

Datasheet 181Processor Pin and Signal Information§ Figure 8-27.BGA Mechanical Package (Sheet 2 of 2)

Datasheet 19Features Summary1.8 Related Documents§ DocumentDocument Number/ LocationPublic SpecificationsAdvanced Configuration and Power Interface Sp

2 DatasheetLegal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

Interfaces20 Datasheet2 InterfacesThis chapter describes the interfaces supported by the processor.2.1 System Memory Interface2.1.1 System Memory Tech

Datasheet 21InterfacesNOTES:1. System memory configurations are based on availability and are subject to change.2. Only Raw Card D SO-DIMMs at 1066 MT

Interfaces22 Datasheet2.1.3.1 Single-Channel ModeIn this mode, all memory cycles are directed to a single-channel. Single-channel mode is used when ei

Datasheet 23InterfacesWhen both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single cha

Interfaces24 Datasheetconnector per channel. For dual-channel modes both channels must have an SO-DIMM connector populated. For single-channel mode, o

Datasheet 25Interfaces2.2 PCI Express InterfaceThis section describes the PCI Express interface capabilities of the processor. See the PCI Express Bas

Interfaces26 Datasheetpackets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transact

Datasheet 27Interfaces2.2.2 PCI Express Configuration MechanismThe PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structur

Interfaces28 Datasheet2.2.3.1 PCI Express Bifurcated ModeWhen bifurcated, the signals which had previously been assigned to Lanes 15:8 of the single x

Datasheet 29Interfaces2.4 Intel® HD Graphics ControllerThis section details the 2D, 3D and video pipeline and their respective capabilities.The integr

Datasheet 3Contents1 Features Summary ...91.1 Introdu

Interfaces30 Datasheet Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing.2.4.1.2 3D Pipeline2.4.1.2.1 Ver

Datasheet 31Interfaces2.4.1.3 Video EngineThe Video Engine handles the non-3D (media/video) applications. It includes support for VLD and MPEG2 decode

Interfaces32 Datasheet2.4.2 Integrated Graphics Display PipesThe integrated graphics controller display pipe can be broken down into three components:

Datasheet 33Interfaces2.4.2.1.3 Cursors A and BCursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration, and are associat

Interfaces34 DatasheetWhen eDP is enabled, the lower logical lanes are still available for standard PCIe devices, using the PEG 0 controller. PEG 0 is

Datasheet 35Interfaces Allow communication of processor thermal and other information to the PECI master. Read averaged Digital Thermal Sensor (DTS)

Technologies36 Datasheet3 Technologies3.1 Intel® Virtualization TechnologyIntel Virtualization Technology (Intel VT) makes a single system appear as m

Datasheet 37TechnologiesTLBs) This avoids flushes on VM transitions to give a lower-cost VM transition timeand an overall reduction in virtualization

Power Management38 Datasheet4 Power ManagementThis chapter provides information on the following power management topics: ACPI States Processor Core

Datasheet 39Power Management4.1.3 Integrated Memory Controller States4.1.4 PCIe Link States4.1.5 DMI States 4.1.6 Integrated Graphics Controller State

4 Datasheet3 Technologies...363.1 Intel® Virt

Power Management40 Datasheet4.1.7 Interface State Combinations4.2 Processor Core Power ManagementWhile executing code, Enhanced Intel SpeedStep Techno

Datasheet 41Power Management4.2.1 Enhanced Intel SpeedStep® TechnologyThe following are the key features of Enhanced Intel SpeedStep Technology: Mult

Power Management42 DatasheetEntry and exit of the C-States at the thread and core level are shown in below figure.While individual threads can request

Datasheet 43Power ManagementNOTE:If enabled, the core C-state will be C1E if all actives cores have also resolved a core C1 state or higher4.2.3 Reque

Power Management44 Datasheet4.2.4 Core C-statesThe following are general rules for all core C-states, unless specified otherwise: A core C-State is d

Datasheet 45Power Management4.2.4.4 Core C6 StateIndividual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6) i

Power Management46 DatasheetThe processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor

Datasheet 47Power Management4.2.5.1 Package C0The normal operating state for the processor. The processor remains in the normal state when at least on

Power Management48 DatasheetNo notification to the system occurs upon entry to C1/C1E.4.2.5.3 Package C3 StateA processor enters the package C3 low po

Datasheet 49Power Management4.3.1 Disabling Unused System Memory OutputsAny system memory (SM) interface signal that goes to a memory module connector

Datasheet 56.7 DMI...776.8 PLL Signals..

Power Management50 Datasheet4.3.2.3 Dynamic Power Down OperationDynamic power-down of memory is employed during normal operation. Based on idle condit

Datasheet 51Power Management4.5 DMI Power ManagementActive power management support using L0s/L1 state.4.6 Integrated Graphics Power Management4.6.1 I

Power Management52 Datasheet4.7 Thermal Power Management  See Section 5, Thermal Management on page 53 for all graphics thermal power management-re

Datasheet 53Thermal Management5 Thermal ManagementA multi-chip package (MCP) processor requires a thermal solution to maintain temperatures of the pro

Thermal Management54 Datasheetsystem that is shipped with the customers platform and Intel Graphics Dynamic Frequency is enabled, the Intel Turbo Boo

Datasheet 55Thermal Management5 Processor core and integrated graphics and memory controller junction temperatures are monitored by their respective D

Thermal Management56 DatasheetTable 5-17.Intel Celeron Mobile Processor P4000 Series Dual-Core SV Thermal Power Specifications5.1.3 Idle Power Specifi

Datasheet 57Thermal ManagementTable 5-19.35 W Standard Voltage (SV) Processor Idle Power5.1.4 Intelligent Power Sharing Control OverviewBased upon kno

Thermal Management58 Datasheet5.1.5 Component Power Measurement/Estimation ErrorThe processor input pin (ISENSE) informs the processor core of how muc

Datasheet 59Thermal Management Adjusting the operating frequency (via the core ratio multiplier) and input voltage (via the VID signals).  Modulatin

6 DatasheetFigure 8-19 Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant)...108Figure 8-20 Socket-G (rPGA988A) Pinmap (Top View

Thermal Management60 DatasheetOnce a target frequency/bus ratio is resolved, the processor core will transition to the new target automatically. On a

Datasheet 61Thermal ManagementIf a processor load-based Enhanced Intel SpeedStep Technology/P-state transition (through MSR write) is initiated while

Thermal Management62 DatasheetCode execution is halted in C1-C6. Therefore temperature cannot be read via the processor MSR without bringing a core ba

Datasheet 63Thermal Management5.2.1.3.2 Voltage Regulator ProtectionPROCHOT# may be used for thermal protection of voltage regulators (VR). System des

Thermal Management64 Datasheetbi-directional PROCHOT#. Platforms must not rely on software usage of this mechanism to limit the processor temperature.

Datasheet 65Thermal Management5.2.2 Integrated Graphics and Memory Controller Thermal FeaturesThe integrated graphics and memory controller provides t

Thermal Management66 Datasheet5.2.2.1.3 Catastrophic Trip PointThis trip point is set at the temperature at which the integrated graphics and memory c

Datasheet 67Thermal Managementdigital thermal sensor (DTS) and initiates duty cycle throttling to delay memory transactions and thereby reducing MCH p

Thermal Management68 Datasheetcontroller will shut off its internal clocks (thus halting program execution) in an attempt to reduce the core junction

Datasheet 69Thermal Management5.2.3.2 Processor Thermal Data Sample Rate and FilteringThe processor digital thermal sensor (DTS) provides an improved

Datasheet 7Table 7-40 Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications96Table 7-41 Processor Uncore I/O Buffer Supply D

Signal Description70 Datasheet6 Signal DescriptionThis chapter describes the processor signals. They are arranged in functional groups according to th

Datasheet 71Signal Description6.1 System Memory InterfaceTable 6-21.Memory Channel A (Sheet 1 of 2)Signal Name Description Direction/Buffer TypeSA_BS[

Signal Description72 DatasheetSA_CKE[1:0] Clock Enable: (1 per rank) Used to:- Initialize the SDRAMs during power-up- Power-down SDRAM ranks- Place al

Datasheet 73Signal Description6.2 Memory Reference and CompensationSB_MA[15:0] Memory Address: These signals are used to provide the multiplexed row a

Signal Description74 Datasheet6.3 Reset and Miscellaneous SignalsTable 6-24.Reset and Miscellaneous Signals (Sheet 1 of 2)Signal Name Description Dire

Datasheet 75Signal Description6.4 PCI Express Graphics Interface SignalsPRDY# PRDY#: A processor output used by debug tools to determine processor deb

Signal Description76 Datasheet6.5 Embedded DisplayPort (eDP)6.6 Intel Flexible Display Interface SignalsEmbedded Display Port SignalsSignal Name Descr

Datasheet 77Signal Description6.7 DMI6.8 PLL SignalsFDI_TX[7:4]FDI_TX#[7:4]Intel® Flexible Display Interface Transmit Differential Pair - Pipe BOFDIFD

Signal Description78 Datasheet6.9 TAP SignalsTable 6-29.TAP SignalsSignal Name Description Direction/Buffer TypeTCK TCK (Test Clock): Provides the clo

Datasheet 79Signal Description6.10 Error and Thermal ProtectionTable 6-30.Error and Thermal ProtectionSignal Name Description Direction/Buffer TypeCAT

8 DatasheetRevision History§ Revision NumberDescription Revision Date001 Initial release October 2010

Signal Description80 Datasheet6.11 Power SequencingTable 6-31.Power SequencingSignal Name Description Direction/Buffer TypeVCCPWRGOOD_0VCCPWRGOOD_1VCC

Datasheet 81Signal Description6.12 Processor Power SignalsTable 6-32.Processor Power Signals (Sheet 1 of 3)Signal Name Description Direction/Buffer Ty

Signal Description82 DatasheetVID[6]VID[5:3]/CSC[2:0]VID[2:0]/MSID[2:0]VID[6:0] (Voltage ID) Pins: Used to support automatic selection of power supply

Datasheet 83Signal Description6.13 Ground and NCTF6.14 Processor Internal Pull Up/Pull DownGFX_DPRSLPVR GPU output signal to Intel MVP6.5 compliant VR

Signal Description84 Datasheet§ TDI_M Pull Up VTT 44 - 55 kPREQ# Pull Up VTT 44 - 55 kCFG[17:0] Pull Up VTT 5 - 14 kTable 6-34.Processor Internal Pull

Datasheet 85Electrical Specifications7 Electrical Specifications7.1 Power and Ground PinsThe processor has VCC, VTT, VDDQ, VCCPLL, VAXG and VSS (groun

Electrical Specifications86 Datasheet7.3.1 PLL Power SupplyAn on-die PLL filter solution is implemented on the processor. Refer to Table 7-35 for DC s

Datasheet 87Electrical Specifications0 0 0 0 1 1 1 1.41250 0 0 1 0 0 0 1.40000 0 0 1 0 0 1 1.38750 0 0 1 0 1 0 1.37500 0 0 1 0 1 1 1.36250 0 0 1 1 0 0

Electrical Specifications88 Datasheet0 1 1 0 1 0 1 0.83750 1 1 0 1 1 0 0.82500 1 1 0 1 1 1 0.81250 1 1 1 0 0 0 0.80000 1 1 1 0 0 1 0.78750 1 1 1 0 1 0

Datasheet 89Electrical Specifications1 1 0 0 0 1 1 0.26251 1 0 0 1 0 0 0.25001 1 0 0 1 0 1 0.23751 1 0 0 1 1 0 0.22501 1 0 0 1 1 1 0.21251 1 0 1 0 0 0

Datasheet 9Features Summary1 Features Summary1.1 IntroductionIntel® Celeron® P4000 and U3000 mobile processor seriesis the next generation of 64-bit,

Electrical Specifications90 DatasheetNOTES:1. MSID[2:0] signals are provided to indicate the maximum platform capability to the processor.2. MSID is u

Datasheet 91Electrical Specifications7.6 Signal GroupsSignals are grouped by buffer type and similar characteristics as listed in Table 7-37. The buff

Electrical Specifications92 DatasheetControl SidebandSingle Ended (ja) Asynchronous CMOS InputVCCPWRGOOD_0, VCCPWRGOOD_1, VTTPWRGOOD Single Ended (jb)

Datasheet 93Electrical SpecificationsNOTES:1. Refer to Chapter 6 for signal description details.2. SA and SB refer to DDR3 Channel A and DDR3 Channel

Electrical Specifications94 Datasheet7.8 Absolute Maximum and Minimum RatingsTable 7-38 specifies absolute maximum and minimum ratings. At conditions

Datasheet 95Electrical Specificationsdevice storage conditions for a sustained period of time. At conditions outside sustained limits, but within abso

Electrical Specifications96 Datasheet7.10.1 Voltage and Current SpecificationsNOTES:1. Unless otherwise noted, all specifications in this table are ba

Datasheet 97Electrical SpecificationsFigure 7-13.Active VCC and ICC Loadline (PSI# Asserted) Figure 7-14.Active VCC and ICC Loadline (PSI# Not Asserte

Electrical Specifications98 DatasheetNOTES:1. The voltage specification requirements are defined across at the socket motherboard pinfield vias on the

Datasheet 99Electrical SpecificationsNOTES:1. These are pre-silicon estimates and are subject to change.2. Minimum values assume Graphics Render C-sta