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Thermal Management
60 Datasheet
Once a target frequency/bus ratio is resolved, the processor core will transition to the
new target automatically.
On an upward operating point transition, the voltage transition precedes the
frequency transition.
On a downward transition, the frequency transition precedes the voltage transition.
When transitioning to a target core operating voltage, a new VID code to the voltage
regulator is issued. The voltage regulator must support dynamic VID steps to support
this method.
During the voltage change:
It will be necessary to transition through multiple VID steps to reach the target
operating voltage.
Each step is 12.5 mV for Intel MVP-6.5 compliant VRs.
The processor continues to execute instructions. However, the processor will halt
instruction execution for frequency transitions.
Figure 5-12.Frequency and Voltage Ordering
- P4000 and U3000 Series 1
- 2 Datasheet 2
- Contents 3
- 4 Datasheet 4
- Datasheet 5 5
- 6 Datasheet 6
- Datasheet 7 7
- Revision History 8
- 1 Features Summary 9
- Platform 10
- Processor 10
- 1.2 Processor Feature Details 11
- 1.3 Interfaces 11
- 1.3.2 PCI Express* 12
- Datasheet 13 13
- Features Summary 13
- 14 Datasheet 14
- 1.4 Power Management Support 15
- 1.6 Package 16
- 1.7 Terminology 17
- 1.8 Related Documents 19
- 2 Interfaces 20
- tCL = CAS Latency 21
- CWL = CAS Write Latency 21
- 2.1.3.1 Single-Channel Mode 22
- Datasheet 23 23
- Interfaces 23
- 2.1.5.2 Command Overlap 24
- 2.2 PCI Express Interface 25
- 2.2.1.1 Transaction Layer 26
- 2.2.1.2 Data Link Layer 26
- 2.2.1.3 Physical Layer 26
- Datasheet 27 27
- 2.3.1 DMI Error Flow 28
- 2.3.3 DMI Link Down 28
- Includes Hierarchal-Z 29
- 2.4.1.2 3D Pipeline 30
- Data alignment 31
- Display Planes 32
- Display Pipes 32
- 2.4.2.2 Display Pipes 33
- 2.4.2.3 Display Ports 33
- 2.6 Interface Clocking 35
- 3 Technologies 36
- ® VT-x Features 36
- Graphics driver 37
- 4 Power Management 38
- 4.1.4 PCIe Link States 39
- 4.1.5 DMI States 39
- 4.2.2 Low-Power Idle States 41
- C1 C1E C6C3 42
- 4.2.4 Core C-states 44
- 4.2.5 Package C-States 45
- 4.2.5.1 Package C0 47
- 4.2.5.2 Package C1/C1E 47
- 4.3 IMC Power Management 48
- Reduced power consumption 49
- 4.4 PCIe Power Management 50
- 4.5 DMI Power Management 51
- 4.7 Thermal Power Management 52
- 5 Thermal Management 53
- 4,5,10,12 55
- Thermal Management 58
- 58 Datasheet 58
- Datasheet 59 59
- 60 Datasheet 60
- Datasheet 61 61
- 5.2.1.3 PROCHOT# Signal 62
- 5.2.1.4 On-Demand Mode 63
- 5.2.1.5 THERMTRIP# Signal 64
- Features 65
- 66 Datasheet 66
- 5.2.2.4 THERMTRIP# Operation 67
- 68 Datasheet 68
- Datasheet 69 69
- 6 Signal Description 70
- 6.1 System Memory Interface 71
- 6.8 PLL Signals 77
- 6.9 TAP Signals 78
- 6.11 Power Sequencing 80
- 6.12 Processor Power Signals 81
- 6.13 Ground and NCTF 83
- 7 Electrical Specifications 85
- 7.3.1 PLL Power Supply 86
- 7.6 Signal Groups 91
- Table 7-37.Signal Groups 92
- (Sheet 2 of 3) 92
- 7.10 DC Specifications 95
- Specifications 96
- 10mV= RIPPLE 97
- Slope = LL 99
- +/-VID*2.2% 99
- Symbol Parameter 100
- Min Typ Max Units Notes 100
- DC Specifications 103
- 8 Processor Pin and Signal 105
- Information 105
- 106 Datasheet 106
- Datasheet 107 107
- 108 Datasheet 108
- Datasheet 109 109
- List by Pin Number 110
- List by Pin Name 124
- Datasheet 138 138
- Datasheet 139
- Datasheet 140 140
- 143 Datasheet 143
- 145 Datasheet 145
- 147 Datasheet 147
- 149 Datasheet 149
- 151 Datasheet 151
- 153 Datasheet 153
- 155 Datasheet 155
- 157 Datasheet 157
- 159 Datasheet 159
- 161 Datasheet 161
- 163 Datasheet 163
- 165 Datasheet 165
- 167 Datasheet 167
- 169 Datasheet 169
- 171 Datasheet 171
- 173 Datasheet 173
- 175 Datasheet 175
- 177 Datasheet 177
- List by Ball Number 178
- (Sheet 37 of 37) 178
- Datasheet 179 179
- 180 Datasheet 180
- Datasheet 181 181
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