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Mobile Intel® Celeron® Processor (0.18µ and 0.13µ) Specification Update November 2006 Version 054 R Notice: The mobile Intel® Celeron

R 10 Mobile Intel® Celeron® Processor Specification Update Figure 4. Mobile Intel® Celeron® Processor 0.18µ (Micro-FCBGA) Markings Legal Requireme

R Mobile Intel® Celeron® Processor Specification Update 11 Figure 6. Mobile Intel® Celeron® Processor 0.13µ (Micro-FCBGA) Markings Figure 7. Inte

R 12 Mobile Intel® Celeron® Processor Specification Update Example: PMN70001201AA The PTC will consist of 13 characters as identified in the above e

R Mobile Intel® Celeron® Processor Specification Update 13 Summary of Changes The following table indicates the Errata, Documentation Changes, Specif

R 14 Mobile Intel® Celeron® Processor Specification Update S = 64-bit Intel® Xeon™ processor with 800 MHz system bus T = Mobile Intel® Pentium®

R Mobile Intel® Celeron® Processor Specification Update 15 NO. BA2 PA2 MA2 BB0 PB0 MB0 BC0 PC0 MC0 BD0 PD0 FBDO FPDO FBA1 FPA1 FBB1 FPB1 Plans ERRATA

R 16 Mobile Intel® Celeron® Processor Specification Update NO. BA2 PA2 MA2 BB0 PB0 MB0 BC0 PC0 MC0 BD0 PD0 FBDO FPDO FBA1 FPA1 FBB1 FPB1 Plans ERRAT

R Mobile Intel® Celeron® Processor Specification Update 17 NO. BA2 PA2 MA2 BB0 PB0 MB0 BC0 PC0 MC0 BD0 PD0 FBDO FPDO FBA1 FPA1 FBB1 FPB1 Plans ERRATA

R 18 Mobile Intel® Celeron® Processor Specification Update NO. BA2 PA2 MA2 BB0 PB0 MB0 BC0 PC0 MC0 BD0 PD0 FBDO FPDO FBA1 FPA1 FBB1 FPB1 Plans ERRAT

R Mobile Intel® Celeron® Processor Specification Update 19 NO. BA2 PA2 MA2 BB0 PB0 MB0 BC0 PC0 MC0 BD0 PD0 FBDO FPDO FBA1 FPA1 FBB1 FPB1 Plans ERRATA

R 2 Mobile Intel® Celeron® Processor Specification Update INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, E

R 20 Mobile Intel® Celeron® Processor Specification Update NO. BA2 PA2 MA2 BB0 PB0 MB0 BC0 PC0 MC0 BD0 PD0 FBDO FPDO FBA1 FPA1 FBB1 FPB1 Plans ERRAT

R Mobile Intel® Celeron® Processor Specification Update 21 Identification Information The mobile Intel® Celeron® processor (0.18µ and 0.13µ) can be i

R 22 Mobile Intel® Celeron® Processor Specification Update S-Spec Product Stepping CPU Signature Speed (MHz) Core/Bus Integrated L2 Size (Kbytes) Pa

R Mobile Intel® Celeron® Processor Specification Update 23 Table 2. Identification information for Mobile Intel® Celeron® Processor (0.18μ) Micro-FC

R 24 Mobile Intel® Celeron® Processor Specification Update 4. VID[4:0] = 10001; VCC_CORE = 0.95V 5. VID[4:0] = 11000; VCC_CORE = 1.40V S. Support

R Mobile Intel® Celeron® Processor Specification Update 25 Errata M1. WBINVD May Lock Write Out Buffer Problem: The FP Data Operand Pointer is the

R 26 Mobile Intel® Celeron® Processor Specification Update Case 2: In the second breakpoint reporting failure case, if a MOVSS or POPSS instruction

R Mobile Intel® Celeron® Processor Specification Update 27 M4. Double ECC Error on Read May Result in BINIT# Problem: For this erratum to occur, the

R 28 Mobile Intel® Celeron® Processor Specification Update Implication: Inexact-result exceptions are commonly masked or ignored by applications, a

R Mobile Intel® Celeron® Processor Specification Update 29 Status: For the steppings affected see the Summary of Changes at the beginning of this se

R Mobile Intel® Celeron® Processor Specification Update 3 Contents Revision History...

R 30 Mobile Intel® Celeron® Processor Specification Update M12. BTMs May Be Corrupted During Simultaneous L1 Cache Line Replacement Problem: When B

R Mobile Intel® Celeron® Processor Specification Update 31 M15. FP Data Operand Pointer May Not Be Zero After Power On or Reset Problem: The FP Data

R 32 Mobile Intel® Celeron® Processor Specification Update In the example, EAX is forced to contain 0 by the XOR or SUB instructions. Since the four

R Mobile Intel® Celeron® Processor Specification Update 33 Workaround: Code which performs loads from memory that has side-effects can effectively wo

R 34 Mobile Intel® Celeron® Processor Specification Update V86 mode before continuing. If the exception did occur in V86 mode, the exception may be

R Mobile Intel® Celeron® Processor Specification Update 35 M24. SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment Selector” to SS and C

R 36 Mobile Intel® Celeron® Processor Specification Update Status: For the steppings affected see the Summary of Changes at the beginning of this s

R Mobile Intel® Celeron® Processor Specification Update 37 erroneously causes the eviction of a line from the IFU at a time when the processor is exp

R 38 Mobile Intel® Celeron® Processor Specification Update M34. Cache Coherency May Be Lost If Snoop Occurs During Cache Line Invalidation Problem:

R Mobile Intel® Celeron® Processor Specification Update 39 a corresponding bus transaction, causing the processor to hang (livelock). The exact circ

R 4 Mobile Intel® Celeron® Processor Specification Update Revision History Revision Number Description Date -001 Initial release February 2000 -002

R 40 Mobile Intel® Celeron® Processor Specification Update M41. L2_DBUS_BUSY Performance Monitoring Counter Will Not Count Writes Problem: The L2_

R Mobile Intel® Celeron® Processor Specification Update 41 Software using unsynchronized XMC to modify the instruction byte stream of a processor may

R 42 Mobile Intel® Celeron® Processor Specification Update Status: For the steppings affected see the Summary of Changes at the beginning of this s

R Mobile Intel® Celeron® Processor Specification Update 43 1. XOR EAX, EAX or SUB EAX, EAX 2. MOVSX AX, BL or MOVSX AX, byte ptr <memory address

R 44 Mobile Intel® Celeron® Processor Specification Update Status: For the steppings affected see he Summary of Changes at the beginning of this se

R Mobile Intel® Celeron® Processor Specification Update 45 2. The memory accessing instruction is immediately followed by a waiting floating-point o

R 46 Mobile Intel® Celeron® Processor Specification Update Problem: A small window of time exists in which internal timing conditions in the proces

R Mobile Intel® Celeron® Processor Specification Update 47 M57. Intermittent Power-on Failure due to Uninitialized Processor Internal Nodes Problem:

R 48 Mobile Intel® Celeron® Processor Specification Update Implication: When the OS recovers from the double fault handler, the processor will no l

R Mobile Intel® Celeron® Processor Specification Update 49 M64. Machine Check Exception may Occur When Interleaving Code Between Different Memory Typ

R Mobile Intel® Celeron® Processor Specification Update 5 Revision Number Description Date -019 Updated Summary of Changes; Added Erratum M68 and M6

R 50 Mobile Intel® Celeron® Processor Specification Update Workaround: Software should always poll the Delivery Status bit in the APIC ICR and ensur

R Mobile Intel® Celeron® Processor Specification Update 51 Workaround: Do not use boundary scan when DPSLP# is asserted low. Status: For the steppin

R 52 Mobile Intel® Celeron® Processor Specification Update M73. Lock Data Access that Spans Two Pages May Cause the System to Hang Problem: An in

R Mobile Intel® Celeron® Processor Specification Update 53 Workaround: There is no workaround for single step operation in commercially available s

R 54 Mobile Intel® Celeron® Processor Specification Update M80. Page with PAT (Page Attribute Table) Set to USWC (Uncacheable Speculative Write Com

R Mobile Intel® Celeron® Processor Specification Update 55 Implication: When this erratum occurs, the values for FPUDataPointer in the saved floatin

R 56 Mobile Intel® Celeron® Processor Specification Update M87. The Processor May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TS

R Mobile Intel® Celeron® Processor Specification Update 57 M90. Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM Problem: After

R 58 Mobile Intel® Celeron® Processor Specification Update Status: For the steppings affected, see the Summary Tables of Changes M93. The BS Flag i

R Mobile Intel® Celeron® Processor Specification Update 59 Specification Changes There are no specification changes. §

R 6 Mobile Intel® Celeron® Processor Specification Update Revision Number Description Date -040 Added errata M77-79 October 2004 -041 Added errata M

R 60 Mobile Intel® Celeron® Processor Specification Update Specification Clarifications The Specification Clarifications listed in this section appl

R Mobile Intel® Celeron® Processor Specification Update 61 6. PDSLP is Deep Sleep power. M2. SPECIFICATION CLARIFICATION WITH RESPECT TO TIME STAMP

R 62 Mobile Intel® Celeron® Processor Specification Update NOTE To determine average processor clock frequency, Intel recommends the use of Perform

R Mobile Intel® Celeron® Processor Specification Update 63 • Time-stamp counter — Measures clock cycles in which the physical processor is

R 64 Mobile Intel® Celeron® Processor Specification Update Documentation Changes There are no Documentation Changes for this month. §

R Mobile Intel® Celeron® Processor Specification Update 7 Preface This document is an update to the specifications contained in the documents listed

R 8 Mobile Intel® Celeron® Processor Specification Update Nomenclature S-Spec Number is a five-digit code used to identify products. Products are di

R Mobile Intel® Celeron® Processor Specification Update 9 Figure 2. Mobile Intel® Celeron® Processor (BGA2) Markings (Supplier Lot ID +SER#)Legal(YY