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Document Number: 324208-005USIntel® Atom™ Processor E6xx SeriesDatasheetApril 2013Revision 005US

ContentsIntel® Atom™ Processor E6xx Series Datasheet1011.3.6.3 Automatic Rotation Mode (Equal Priority Devices) ...22111.3.6.4 Sp

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet100 Table 97. D0h: GVD.PMCAP – Power Management CapabilitiesSize: 32 bit Defa

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet101 00b RWSMI_OR_SCI_EVENTMCE: If MCS=1, setting this bit causes an SCI. If M

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet102 7.7.2 D3:F0 PCI Configuration Registers23 :16 00h RW SCRATCH_2Software scr

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet1037.7.2.1 Offset 00h: ID – Identifiers7.7.2.2 Offset 04h: CMD – PCI Command34

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet1047.7.2.3 Offset 06h: STS - PCI Status7.7.2.4 Offset 08h: RID - Revision Iden

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet1057.7.2.6 Offset 0Eh: HDR - Header Type7.7.2.7 Offset 10h: MMADR - Memory Map

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet1067.7.2.8 Offset 14h: IOBAR - I/O Base AddressThis register provides the base

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet1077.7.2.12 Offset 58h: SSRW - Software Scratch Read Write7.7.2.13 Offset 60h:

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet1087.7.2.16 Offset 94h: MA - Message Address7.7.2.17 Offset 98h: MD - Message

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet1097.7.2.19 Offset E0h: SWSCISMI - Software SCI/SMI7.7.2.20 Offset E4h: ASLE -

ContentsIntel® Atom™ Processor E6xx Series Datasheet1111.7.2.1 Offset 20h: RGEN – Resume Well GPIO Enable... 23711.7.2.2 Offs

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet1107.7.2.22 Offset F4h: LBB - Legacy Backlight Brightness§ §03 : 02 01 RWGFX2X

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1118.0 PCI Express*8.1 Functional DescriptionThere are four PCI Express* root ports available

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet112If RCTL.PIE is set, an interrupt is generated. If RCTL.PIE is not set, an SCI/SMI_B may be

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1138.2.1.1 VID — Vendor IdentificationThis register combined with the Device Identification re

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1148.2.1.3 CMD — PCI Command8.2.1.4 PSTS — Primary StatusThis register reports the occurrence

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1158.2.1.5 RID — Revision IdentificationThis register contains the revision number of the devi

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1168.2.1.7 CLS — Cache Line Size8.2.1.8 HTYPE — Header TypeThis register identifies the header

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1178.2.1.11 SBBN — Subordinate Bus NumberThis register identifies the subordinate bus (if any)

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1188.2.1.13 IOLIMIT — I/O Limit AddressThis register controls the CPU to PCI Express* I/O acce

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1198.2.1.15 MB — Memory Base AddressAccesses that are within the ranges specified in this regi

ContentsIntel® Atom™ Processor E6xx Series Datasheet1211.10.1Overview...

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1208.2.1.18 PML — Prefetchable Memory Limit AddressThis register controls the CPU to PCI Expre

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1218.2.1.21 IPIN — Interrupt PinThis register specifies which interrupt pin this device uses.8

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1228.2.2 Root Port Capability StructureThe following registers follow the PCI Express* capabil

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1238.2.2.1 CLIST — Capabilities List8.2.2.2 XCAP — PCI Express* Capabilities8.2.2.3 DCAP — Dev

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1248.2.2.4 DCTL — Device Control11 : 09 111b RO E1ALEndpoint L1 Acceptable Latency: This indic

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1258.2.2.5 DSTS — Device Status8.2.2.6 LCAP — Link CapabilitiesTable 154. Offset 4Ah: DSTS — D

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1268.2.2.7 LCTL — Link Control8.2.2.8 LSTS — Link StatusTable 156. Offset 50h: LCTL — Link Con

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1278.2.2.9 SLCAP — Slot Capabilities8.2.2.10 SLCTL — Slot ControlTable 158. Offset 54h: SLCAP

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1288.2.2.11 SLSTS — Slot Status03 0b RW PDEPresence Detect Changed Enable: When set, enables t

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1298.2.2.12 RCTL — Root Control8.2.2.13 RCAP — Root Capabilities8.2.2.14 RSTS — Root StatusTab

ContentsIntel® Atom™ Processor E6xx Series Datasheet13Tables1 PCI Devices and Functions...

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1308.2.3 PCI Bridge Vendor Capability8.2.3.1 SVCAP — Subsystem Vendor Capability8.2.3.2 SVID —

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1318.2.4.1 PMCAP — Power Management Capability ID8.2.4.2 PMC — PCI Power Management Capabiliti

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1328.2.5 Port Configuration08 0 RW PMEEPME Enable: The root port takes no action on this bit,

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1338.2.5.1 MPC — Miscellaneous Port ConfigurationTable 172. Offset D8h: MPC — Miscellaneous Po

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1348.2.5.2 SMSCS — SMI / SCI StatusTable 173. Offset DCh: SMSCS — SMI / SCI StatusSize: 32 bit

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet1358.2.6 Miscellaneous Configuration8.2.6.1 FD — Functional Disable§ §Table 174. Miscellaneous

PCI Express*Intel® Atom™ Processor E6xx Series Datasheet136

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1379.0 Intel® High Definition Audioβ D27:F09.1 OverviewThe Intel® High

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet138Prior to the physical undocking process the user normally requests

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1399.2.2 Undock SequenceThere are two possible undocking scenarios. Th

ContentsIntel® Atom™ Processor E6xx Series Datasheet1454 312Ch: D23IP – Device 23 Interrupt Pin ...

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1409.2.4 External Pull-Ups/Pull-DownsThe following table shows the res

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1410C 0C CLS Cache Line Size 00h RW0D 0D LT Latency Timer 00h RO0E 0E

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1429.3.1.1 Offset 00h: VID – Vendor Identification9.3.1.2 Offset 02h:

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1439.3.1.4 Offset 06h: PCISTS – PCI Status Register9.3.1.5 Offset 08h:

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1449.3.1.7 Offset 0Ch: CLS - Cache Line Size Register9.3.1.8 Offset 0D

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1459.3.1.11 Offset 14h: UBAR – Upper Base Address Register9.3.1.12 Off

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1469.3.1.13 Offset 2Eh: SID—Subsystem IdentifierThis register should b

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1479.3.1.16 Offset 3Dh – INTPN—Interrupt Pin Register9.3.1.17 Offset 4

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1489.3.1.19 Offset 4Dh – DCKSTS—Docking Status Register9.3.1.20 Offset

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1499.3.1.22 Offset 54h: PM_CTL_STS - Power Management Control And Stat

ContentsIntel® Atom™ Processor E6xx Series Datasheet15109 Offset 0Eh: HDR - Header Type...

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1509.3.1.23 Offset 60h: MSI_CAPID - MSI Capability ID Register9.3.1.24

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1519.3.1.27 Offset 70h: PCIE_CAPID – PCI Express* Capability Identifie

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1529.3.1.31 Offset 7Ah: DEVS – Device Status Register9.3.1.32 Offset F

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1539.3.1.33 Offset 100h: VCCAP – Virtual Channel Enhanced Capability H

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1549.3.1.35 Offset 108h: PVCCAP2 – Port VC Capability Register 29.3.1.

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1559.3.1.39 Offset 114h: VC0CTL – VC0 Resource Control Register9.3.1.4

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1569.3.1.43 Offset 126h: VC1STS – VC1 Resource Status Register9.3.1.44

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1579.3.1.46 Offset 140h: L1DESC – Link 1 Description Register9.3.1.47

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet158These memory mapped registers must be accessed a byte, word, or Dwo

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet15998 9B ISD0BDPL ISD0 Buffer Descriptor List Pointer 0000_0000h RW, R

ContentsIntel® Atom™ Processor E6xx Series Datasheet16164 PCI Bridge Vendor Capability...

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1609.3.2.1.1 Offset 00h: GCAP – Global Capabilities Register9.3.2.1.2

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1619.3.2.1.3 Offset 03h: VMAJ – Major Version9.3.2.1.4 Offset 04h: OUT

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1629.3.2.1.6 Offset 08h: GCTL – Global Control06 :00 1Dh RO INPAYInput

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1639.3.2.1.7 Offset 0Ch: WAKEEN – Wake Enable00 0 RW CRST_BController

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1649.3.2.1.8 Offset 0Eh: STATESTS – State Change Status9.3.2.1.9 Offse

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1659.3.2.1.10 Offset 14h: ECAP - Extended Capabilities9.3.2.1.11 Offse

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1669.3.2.1.13 Offset 24h: INTSTS - Interrupt Status Register9.3.2.1.14

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1679.3.2.1.15 Offset 38h: SSYNC –Stream Synchronization RegisterTable

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1689.3.2.1.16 Offset 40h: CORBBASE - CORB Base Address Register9.3.2.1

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1699.3.2.1.19 Offset 4Ch: CORBCTL - CORB Control Register9.3.2.1.20 Of

ContentsIntel® Atom™ Processor E6xx Series Datasheet17219 120h: VC1CTL – VC1 Resource Control Register ...

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1709.3.2.1.21 Offset 4Eh: CORBSIZE - CORB Size Register9.3.2.1.22 Offs

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1719.3.2.1.24 Offset 5Ah: RINTCNT – Response Interrupt Count Register9

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1729.3.2.1.26 Offset 5Dh: RIRBSTS - RIRB Status Register9.3.2.1.27 Off

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1739.3.2.1.28 Offset 60h: IC – Immediate Command Register9.3.2.1.29 Of

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1749.3.2.1.31 Offset 70h: DPBASE – DMA Position Base Address Register0

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1759.3.2.1.32 Offset 80h, A0h, C0h, E0h: ISD0CTL, ISD1CTL, OSD0CTL, OS

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1769.3.2.1.33 Offset 83h, A3h, C3h, E3h: ISD0STS, ISD1STS, OSD0STS, OS

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1779.3.2.1.34 Offset 84h, A4h, C4h, E4h: ISD0LPIB, ISD1LPIB, OSD0LPIB,

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1789.3.2.1.37 Offset 8Eh, AEh, CEh, EEh: ISD0FIFOW, ISD1FIFOW, OSD0FIF

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1799.3.2.1.38,Offset 90h, B0h: ISD0FIFOS, ISD1FIFOS – Input Stream Des

ContentsIntel® Atom™ Processor E6xx Series Datasheet18266 98h, B8h, D8h, F8h: ISD0BDPL, ISD1BDPL, OSD0BDPL, OSD1BDPL – Input/OutputStream Descriptor [

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1809.3.2.1.40 Offset 92h, B2h, D2h, F2h: ISD0FMT, ISD1FMT, OSD0FMT, OS

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1819.3.2.1.41 Offset 98h, B8h, D8h, F8h: ISD0BDPL, ISD1BDPL, OSD0BDPL,

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1829.3.2.1.42 Offset 1000h: EM1 – Extended Mode 1 Register06 :01 0 RO

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1839.3.2.1.43 Offset 1004h: INRC – Input Stream Repeat Count Register9

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1849.3.2.1.45 Offset 100Ch: FIFOTRK – FIFO Tracking Register9.3.2.1.46

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1859.3.2.1.47 Offset 1030h: EM2 – Extended Mode 2 Register9.3.2.1.48 O

Intel® High Definition Audioβ D27:F0Intel® Atom™ Processor E6xx Series Datasheet1869.3.2.1.49 Offset 2084h, 20A4h, 2104h, 2124h: ISD0LPIBA, ISD1LPIBA,

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet18710.0 LPC Interface (D31:F0) 10.1 Functional OverviewThe LPC controller implements

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet188Note: By default, the LPC clocks are only active when LPC bus transfers occur. Be

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet18910.2.2 CMD—Device Command Register10.2.3 STS—Device Status Register10.2.4 RID—Rev

ContentsIntel® Atom™ Processor E6xx Series Datasheet19318 21h, A1h: ICW4 – Initialization Command Word 4 Register...

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet19010.2.5 CC—Class Code Register10.2.6 HDTYPE—Header Type Register10.2.7 SS—Subsyste

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet19110.3 ACPI Device Configuration10.3.1 SMBA—SMBus Base Address Register10.3.2 GBA—G

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet19210.3.4 GPE0BLK—GPE0_BLK Base Address Register10.3.5 LPCS—LPC Clock Strength Contr

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet19310.3.6 ACTL—ACPI Control Register10.3.7 MC - Miscellaneous Control Register00 Str

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet19423 : 21 0h RO RSVD Reserved20 0 RW BTC6Block Timer Ticks in C6: When set, timer t

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet19510.4 Interrupt Control10.4.1 PxRC—PIRQx Routing Control RegisterOffset 60h routes

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet19610.4.2 SCNT—Serial IRQ Control Register10.4.3 WDTBA-WDT Base Address10.5 FWH Conf

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet19710.5.2 BDE—BIOS Decode Enable27 : 24 0h RW IF0F0-F7 IDSEL: IDSEL to use in FWH cy

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet19810.5.3 BC—BIOS Control Register27 1b RW ED8D8-DF Enable: Enables decoding of BIOS

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet19910.6 Root Complex Register Block Configuration10.6.1 RCBA—Root Complex Base Addre

Intel® Atom™ Processor E6xx Series Datasheet2Legal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO

ContentsIntel® Atom™ Processor E6xx Series Datasheet20373 00h: SPIS - SPI Status...

LPC Interface (D31:F0)Intel® Atom™ Processor E6xx Series Datasheet200

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet20111.0 ACPI Devices11.1 8254 TimerThe 8254 contains three counters which have fixed uses. All

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet202There are two special commands that can be issued to the counters through this register, th

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet20311.1.5.2 Counter Latch CommandThis latches the current count value and is used to ensure th

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet20411.1.5.4 Offset 40h, 41h, 42h: Counter Access Ports Register11.1.6 Timer ProgrammingThe cou

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet2053. Load the least and/or most significant bytes (as required by Control Word bits 5, 4) of

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet206The count is held in the latch until it is read or the counter is reprogrammed. The count i

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet20711.2.1.1 Offset 000h: GCID – General Capabilities and ID11.2.1.2 Offset 010h: GC – General

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet20811.2.1.3 Offset 020h: GIS – General Interrupt Status11.2.1.4 Offset 0F0h: MCV – Main Counte

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet20911.2.1.6 Offset 108h, 128h, 148h: T[0-2]CV – Timer [0-2] Comparator ValueReads to this regi

Revision HistoryIntel® Atom™ Processor E6xx Series Datasheet21Revision HistoryDate Revision DescriptionApril 2013 005Updated Section 5.2, “Introductio

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet21011.2.2 Theory Of Operation11.2.2.1 Non-Periodic Mode – All timersThis mode can be thought o

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet21111.2.2.2 Periodic Mode – Timer 0 onlyWhen set up for periodic mode, when the main counter v

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet21211.2.2.4 Mapping Option #2: Standard Option (GC.LRE cleared)Each timer has its own routing

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet21311.3.2 I/O RegistersThe interrupt controller registers are located at 20h and 21h for the m

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet21411.3.2.2 Offset 21h, A1h: ICW2 – Initialization Command Word 2ICW2 is used to initialize th

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet21511.3.2.3 Offset 21h: MICW3 – Master Initialization Command Word 311.3.2.4 Offset A1h: SICW3

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet21611.3.2.6 Offset 21h, A1h: OCW1 – Operational Control Word 1 (Interrupt Mask)11.3.2.7 Offset

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet217Offset 20h, A0h: OCW3 – Operational Control Word 311.3.2.8 Offset 4D0h: ELCR1 – Master Edge

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet21811.3.2.9 Offset 4D1h: ELCR2 – Slave Edge/Level Control11.3.3 Interrupt Handling11.3.3.1 Gen

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet21911.3.3.3 Hardware/Software Interrupt Sequence1. One or more of the Interrupt Request lines

Revision HistoryIntel® Atom™ Processor E6xx Series Datasheet22§ §October 2010 002Updated Table 2, “Intel® Atom™ Processor E6xx Series SKU for Differen

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet220• Following initialization, an interrupt request (IRQ) input must make a low-to-high transi

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet221Interrupt priorities can be changed in the rotating priority mode.11.3.6.2 Special Fully Ne

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet22211.3.6.6 Edge and Level Triggered ModeIn ISA systems this mode is programmed using bit 3 in

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet223The Special Mask Mode enables all interrupts not masked by a bit set in the Mask Register.

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet22411.4.2 Index RegistersThe registers listed below can be accessed via the IDX register. When

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet22511.4.2.3 Offset 10-11h – 3E-3Fh: RTE[0-23] – Redirection Table EntryOffset: vector 0: 10h-1

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet22611.4.3 Unsupported ModesThese delivery modes are not supported for the following reasons:•

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet22711.4.4.5 Interrupt Delivery Data Value11.4.5 PCI Express* InterruptsWhen external devices t

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet228• Start Frame: SERIRQ line driven low by the interrupt controller to indicate the start of

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet22911.5.5 Serial Interrupts Not SupportedThere are 4 interrupts on the serial stream which are

IntroductionIntel® Atom™ Processor E6xx Series Datasheet231.0 IntroductionThe Intel® Atom™ Processor E6xx Series is the next-generation Intel® archite

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet23011.6 Real Time Clock11.6.1 OverviewThe Real Time Clock (RTC) module provides a battery back

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet23111.6.3.1 Offset 0Ah: Register AThis register is in the RTC well, and is used for general co

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet23211.6.3.2 Offset 0Bh: Register B - General ConfigurationThis register resides in the RTC wel

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet23311.6.3.4 Offset 0Dh: Register D - Flag Register (RTC Well)11.6.4 Update CyclesAn update cyc

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet23411.7 General Purpose I/O11.7.1 Core Well GPIO I/O RegistersThe control for the general purp

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet23511.7.1.2 Offset 04h: CGIO – Core Well GPIO Input/Output Select11.7.1.3 Offset 08h: CGLVL –

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet23611.7.1.5 Offset 10h: CGTNE – Core Well GPIO Trigger Negative Edge Enable11.7.1.6 Offset 14h

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet23711.7.1.8 Offset 1Ch: CGTS – Core Well GPIO Trigger Status11.7.2 Resume Well GPIO I/O Regist

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet23811.7.2.2 Offset 24h: RGIO – Resume Well GPIO Input/Output Select11.7.2.3 Offset 28h: RGLVL

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet23911.7.2.4 Offset 2Ch: RGTPE – Resume Well GPIO Trigger Positive Edge Enable11.7.2.5 Offset 3

IntroductionIntel® Atom™ Processor E6xx Series Datasheet241.1 TerminologyTerm DescriptionACPI Advanced Configuration and Power InterfaceADD2Advanced D

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet24011.7.2.7 Offset 38h: RGSMI – Resume Well GPIO SMI Enable11.7.2.8 Offset 3Ch: RGTS – Resume

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet24111.8 SMBus Controller11.8.1 OverviewThe processor provides an SMBus 1.0-compliant host cont

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet24211.8.2.2 Offset 01h: HSTS - Host Status Register02 :00 0 RW CMDCommand: Indicates the comma

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet24311.8.2.3 Offset 02h: HCLK – Host Clock Divider11.8.2.4 Offset 04h: TSA - Transmit Slave Add

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet24411.8.2.6 Offset 06h: HD0 - Host Data 0This field is transmitted in the DATA0 field of an SM

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet245The host controller supports eight command protocols of the SMB interface (see the System M

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet24611.8.5.2 Bus Time Out If there is an error in the transaction, such that a device does not

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet24711.9.4 SPI ProtocolCommunication on the SPI bus is done with a Master – Slave protocol. Typ

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet248The processor only supports Mode 0.Commands, Addresses and Data are shifted most significan

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet249Note:1. Fast Read Protocol is not supported.2. The Auto Address Increment type is not suppo

IntroductionIntel® Atom™ Processor E6xx Series Datasheet251.2 Reference DocumentsSCI System Control Interrupt. SCI is used in the ACPI protocol.SDRAM

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet25011.9.5.2 Offset 00h: SPIS – SPI StatusTable 372. Bus 0, Device 31, Function 0, PCI Register

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet25111.9.5.3 Offset 02h: SPIC – SPI ControlTable 374. 02h: SPIC - SPI ControlSize: 16 bit Defau

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet25211.9.5.4 Offset 04h: SPIA – SPI Address 11.9.5.5 Offset 08h: SPID0 – SPI Data 0Table 375. 0

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet25311.9.5.6 Offset 10h, 18h, 20h, 28h, 30h, 38h, 40h: SPID[0-6] – SPI Data N11.9.5.7 Offset 50

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet25411.9.5.9 Offset 56h: OPTYPE – Opcode Type ConfigurationThis register is not writable when t

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet255It is recommended that BIOS avoid programming Write Enable opcodes in this menu. Malicious

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet25611.9.5.12 Running SPI Cycles from the Host11.9.5.12.1 Memory ReadsMemory Reads to the BIOS

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet257Note that, although the SPI interface may “burst ahead” for up to 64 bytes, the Host Interf

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet25811.9.5.13 Generic Programmed Commands All commands other than the standard (memory) reads m

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet259The processor provides these protections in hardware. Note that it is critical that the har

IntroductionIntel® Atom™ Processor E6xx Series Datasheet261.3 Components OverviewThe Intel® Atom™ Processor E6xx Series incorporates a variety of PCI

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet260Note that once BIOS has locked down the BIOS BAR, this mechanism remains in place until the

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet261The Write process is executed to write bytes to the Flash device. The atomic instructions t

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet262The following table shows the different device write times for doing a 512 kB sector write.

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet2639. Lock down the SPI registers, Offset 00h: SPIS – SPI Status bit 1510.Set Up SMI based wri

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet264Note: Base Address for the Watchdog Timer registers, listed in this section, is configurabl

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet26511.10.3.2 Offset 01h: PV1R1 - Preload Value 1 Register 111.10.3.3 Offset 02h: PV1R2 - Prelo

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet26611.10.3.4 Offset 04h: PV2R0 - Preload Value 2 Register 011.10.3.5 Offset 05h: PV2R1 - Prelo

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet26711.10.3.7 Offset 0Ch: RR0 - Reload Register 011.10.3.8 Offset 0Dh: RR1 - Reload Register 10

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet26811.10.3.9 Offset 10h: WDTCR - WDT Configuration Register11.10.3.10 Offset 14h: DCR0 - Down

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet26911.10.3.11 Offset 15h: DCR1 - Down Counter Register 111.10.3.12 Offset 16h: DCR2 - Down Cou

IntroductionIntel® Atom™ Processor E6xx Series Datasheet271.3.1 Low-Power Intel® Architecture Core• 600 MHz (Ultra Low Power SKU), 1.0 GHz (Entry SKU)

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet27011.10.4 Theory Of Operation11.10.4.1 RTC Well and WDT_TOUT FunctionalityThe WDT_TIMEOUT bit

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet27111.10.4.3 Reload SequenceTo keep the timer from causing an interrupt or driving GPIO[4], th

ACPI DevicesIntel® Atom™ Processor E6xx Series Datasheet272

Absolute Maximum RatingsIntel® Atom™ Processor E6xx Series Datasheet27312.0 Absolute Maximum RatingsTable 401 specifies absolute maximum and minimum r

Absolute Maximum RatingsIntel® Atom™ Processor E6xx Series Datasheet27412.1 Absolute Maximum RatingNotes:1. Refer to a component device that is not as

DC CharacteristicsIntel® Atom™ Processor E6xx Series Datasheet27513.0 DC Characteristics13.1 Signal GroupsThe signal description includes the type of

DC CharacteristicsIntel® Atom™ Processor E6xx Series Datasheet27613.2 Power and Current CharacteristicsTable 403. Thermal Design PowerSymbol Parameter

DC CharacteristicsIntel® Atom™ Processor E6xx Series Datasheet27713.3 General DC CharacteristicsTable 405. Operating Condition Power Supply and Refere

DC CharacteristicsIntel® Atom™ Processor E6xx Series Datasheet278.Table 406. Active Signal DC Characteristics (Sheet 1 of 3)Symbol Parameter Min Nom M

DC CharacteristicsIntel® Atom™ Processor E6xx Series Datasheet279System Memory (CMOS1.8)VILInput Low Voltage -0.4(VCC180/2) – 0.125VVIHInput High Volt

IntroductionIntel® Atom™ Processor E6xx Series Datasheet281.3.4 Video DecodeThe Intel® Atom™ Processor E6xx Series supports MPEG2, MPEG4, VC1, WMV9, H

DC CharacteristicsIntel® Atom™ Processor E6xx Series Datasheet280§ §VIHMaximum input voltage 1.15 V 7, 9, 12VILMinimum input voltage -0.3 V 7, 9, 13R

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet28114.0 Ballout and Package InformationThe Intel® Atom™ Processor E6xx Seri

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet28214.1 Package DiagramsFigure 10. Intel® Atom™ Processor E6xx Series Silic

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet283Figure 11. Intel® Atom™ Processor E6xx Series Package Dimensions

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet28414.2 Ballout Definition and Signal LocationsFigure 12 provides the ballo

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet285Figure 13. Intel® Atom™ Processor E6xx Series Ball Map (Sheet 1 of 5)98

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet286Figure 14. Intel® Atom™ Processor E6xx Series Ball Map (Sheet 2 of 5)16

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet287Figure 15. Intel® Atom™ Processor E6xx Series Ball Map (Sheet 3 of 5)23

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet288Figure 16. Intel® Atom™ Processor E6xx Series Ball Map (Sheet 4 of 5)30

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet289Figure 17. Intel® Atom™ Processor E6xx Series Ball Map (Sheet 5 of 5)37

IntroductionIntel® Atom™ Processor E6xx Series Datasheet291.3.9 Intel® High Definition Audioβ (Intel® HD Audioβ) ControllerThe Intel® High Definition

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet290Table 407. Pin ListPin Name Ball#BCLKPBCLKNBPM_B[0]BPM_B[1]BPM_B[2]BPM_B

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet291M_MA[0]M_MA[1]M_MA[10]M_MA[11]M_MA[12]M_MA[13]M_MA[14]M_MA[2]M_MA[3]M_MA

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet292VCC180VCC180VCC180VCC180SRVCC33RTCVCCAVCCAVCCAVCCA_PEGVCCA_PEGVCCA_PEGVC

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet293VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

Ballout and Package InformationIntel® Atom™ Processor E6xx Series Datasheet294§ §VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

ContentsIntel® Atom™ Processor E6xx Series Datasheet3Contents1.0 Introduction...

IntroductionIntel® Atom™ Processor E6xx Series Datasheet301.3.14 Watchdog Timer (WDT)The Intel® Atom™ Processor E6xx Series supports a user configurab

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet312.0 Signal DescriptionThis chapter provides a detailed description of the signals and

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet322.1 System Memory SignalsTable 4. System Memory SignalsSignal Direction/Type Power Wel

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet332.2 Integrated Display Interfaces2.2.1 LVDS SignalsTable 5. LVDS SignalsSignal Directi

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet342.2.2 Serial Digital Video Output (SDVO) SignalsTable 6. Serial Digital Video Output S

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet352.3 PCI Express* Signals2.4 Intel® High Definition Audioβ Interface SignalsTable 7. PC

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet362.5 LPC Interface SignalsNote: Boot from LPC is not supported.2.6 SMBus Interface Sign

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet372.8 Power Management Interface SignalsTable 12. Power Management Interface SignalsSign

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet382.9 Real Time Clock Interface Signals2.10 JTAG and Debug InterfaceThe JTAG interface i

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet392.11 Miscellaneous Signals and ClocksTable 15. Miscellaneous Signals and Clocks (Sheet

ContentsIntel® Atom™ Processor E6xx Series Datasheet43.8 SPI Interface Signals...

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet40GPIO_BI/OAGTL+CoreGeneral Purpose I/O / External Thermal Sensor: Same pin type as BPM[

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet41VIDEN[1:0]OCMOSCoreVoltage ID Enable: Indicates which voltage is being specified on th

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet422.12 General Purpose I/O2.13 Functional StrapsThe following signals are used to config

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet432.14 Power and Ground SignalsThis section provides power and ground signals for the In

Signal DescriptionIntel® Atom™ Processor E6xx Series Datasheet44§ §VCCD_DPL 1.05 V DPLL dedicated supplyVCCA_PEG 1.05 V Used by PCIe* and SDVOVCCSFR_E

Pin StatesIntel® Atom™ Processor E6xx Series Datasheet453.0 Pin StatesThis chapter describes the states of each Intel® Atom™ Processor E6xx Series sig

Pin StatesIntel® Atom™ Processor E6xx Series Datasheet463.3 Integrated Display Interfaces3.3.1 LVDS Signals3.3.2 Serial Digital Video Output (SDVO) Si

Pin StatesIntel® Atom™ Processor E6xx Series Datasheet473.4 PCI Express* Signals3.5 Intel® High Definition Audioβ Interface SignalsSDVO_TVCLKINPSDVO_T

Pin StatesIntel® Atom™ Processor E6xx Series Datasheet483.6 LPC Interface Signals3.7 SMBus Interface Signals3.8 SPI Interface Signals3.9 Power Managem

Pin StatesIntel® Atom™ Processor E6xx Series Datasheet493.10 Real Time Clock Interface Signals3.11 JTAG and Debug InterfaceThe JTAG interface is acces

ContentsIntel® Atom™ Processor E6xx Series Datasheet56.3 DRAM Partial Writes...

Pin StatesIntel® Atom™ Processor E6xx Series Datasheet503.13 General Purpose I/O3.14 Integrated Termination Resistors§ §Table 32. General Purpose I/O

System Clock DomainsIntel® Atom™ Processor E6xx Series Datasheet514.0 System Clock DomainsThe Intel® Atom™ Processor E6xx Series contains many clock f

System Clock DomainsIntel® Atom™ Processor E6xx Series Datasheet52

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet535.0 Register and Memory MappingThis chapter describes the I/O and memory map

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet54• Control registers are I/O mapped into the processor I/O space that controls

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet55Figure 3. System Address MapTable 36. Memory Map (Sheet 1 of 2)Device Start A

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet56Note: All accesses to addresses within the main memory range will be forwarde

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet575.3.1.2 Variable I/O Address RangeTable 38 shows the variable I/O decode rang

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet585.4 Register Access MethodThe registers and the connected devices can be acce

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet595.4.1.2 IO BARThe Intel® Atom™ Processor E6xx Series uses a programmable base

ContentsIntel® Atom™ Processor E6xx Series Datasheet67.7.2.8 Offset 14h: IOBAR - I/O Base Address ...1067.7.2.9 Of

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet605.5 Bridging and ConfigurationThis describes all registers and base functiona

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet615.5.1.2 Offset 0004h: ESD – Element Self Description5.5.1.3 Offset 0010h: HDD

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet625.5.2 Interrupt Pin ConfigurationThe following registers tell each device whi

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet635.5.2.4 Offset 3120h: D26IP – Device 26 Interrupt Pin5.5.2.5 Offset 3124h: D2

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet645.5.2.8 Offset 3130h: D03IP – Device 3 Interrupt Pin5.5.3 Interrupt Route Con

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet655.5.3.2 Offset 3148h: D27IR – Device 27 Interrupt Route5.5.3.3 Offset 314Ah:

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet665.5.3.5 Offset 314Eh: D24IR – Device 24 Interrupt Route5.5.3.6 Offset 3150h:

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet675.5.3.8 Offset 3162h: D03IR – Device 3 Interrupt Route5.5.4 General Configura

Register and Memory MappingIntel® Atom™ Processor E6xx Series Datasheet68

Memory ControllerIntel® Atom™ Processor E6xx Series Datasheet696.0 Memory Controller6.1 OverviewThe Intel® Atom™ Processor E6xx Series contains an int

ContentsIntel® Atom™ Processor E6xx Series Datasheet78.2.2.9 SLCAP — Slot Capabilities ... 1278.2

Memory ControllerIntel® Atom™ Processor E6xx Series Datasheet706.4.1 Powerdown ModesThe memory controller employs aggressive use of memory power manag

Memory ControllerIntel® Atom™ Processor E6xx Series Datasheet716.6 Supported DRAM ConfigurationsThe memory controller supports a single, 32-bit channe

Memory ControllerIntel® Atom™ Processor E6xx Series Datasheet726.7 Supported DRAM Devices6.8 Supported Rank ConfigurationsTable 69. Supported DDR2 DRA

Memory ControllerIntel® Atom™ Processor E6xx Series Datasheet736.9 Address Mapping and DecodingFor any rank, the address range it implements is mapped

Memory ControllerIntel® Atom™ Processor E6xx Series Datasheet74§ §A[13] R0 R0 R0 R0 R0 R0 R0 R0A[12] B0 B0 B0 B0 B0 B0 B0 B0A[11] C9 C9 C9 C9 C9 C9 C9

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet757.0 Graphics, Video, and Display7.1 Chapter ContentsThis chapter contains th

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet76— 3D peak performance— Fill rate: two pixels per clock— Vertex rate: One tri

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet777.2.3 Vertex ProcessingModern graphics processors perform two main procedure

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet78calculate specular lighting than diffuse lighting, it adds significant detai

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet79four 8-bit values. When considered as four 8-bit values, the integer unit ef

ContentsIntel® Atom™ Processor E6xx Series Datasheet89.3.1.28 Offset 72h: PCIECAP – PCI Express* Capabilities Register...1519.3.1.29 Offset

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet807.3.1.2 Encode Codec SupportThe Intel® Atom™ Processor E6xx Series supports

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet817.4 Video DecodeThe video decode accelerator improves video performance/powe

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet827.4.1.1 Motion CompensationThe entropy encoder or host can write a series of

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet837.4.1.4 Pixel FormatThe pixel format has the name 420PL12YUV8. This consists

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet84LVDS display devices (see Figure 6). Along the display pipe, the display dat

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet85• Supports NV12 data format• 3x3 Panel Fitter shared by two pipes• Support C

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet86Note: The Intel® Atom™ Processor E6xx Series has limited support for a VGA P

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet877.5.2.1 LVDS PortA single LVDS channel only is supported. The single LVDS ch

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet88transmitter port at the dot clock frequency, which is determined by the pane

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet89A maximum pixel clock of 160 MHz is supported on the SDVO interface.7.5.2.4

ContentsIntel® Atom™ Processor E6xx Series Datasheet911.0 ACPI Devices...

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet907.7 Configuration Registers7.7.1 D2:F0 PCI Configuration RegistersTable 76.

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet91Table 77. 00h: GVD.ID – D2: PCI Device and Vendor ID RegisterSize: 32 bit De

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet9200b RWIO_SPACE_ENABLEIOSE: When set, accesses to this device’s I/O space is

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet93Table 81. 10h: GVD.MMADR – Memory Mapped Address RangeSize: 32 bit Default:

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet94 Table 83. 18h: GVD.GMADR – Graphics Memory Address RangeSize: 32 bit Defau

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet95 Table 85. 2Ch: GVD.SSID – Subsystem IdentifiersSize: 32 bit Default: 0000

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet96 Table 88. 50h: GVD.MGGC – Graphics ControlSize: 32 bit Default: 00300000h P

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet97 Table 89. 5Ch: GVD.BSM – Base of Stolen MemorySize: 32 bit Default: 00000

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet98 22 :20 000b RWMULTIPLE_MESSAGE_ENABLEMME: This field is RW for software co

Graphics, Video, and DisplayIntel® Atom™ Processor E6xx Series Datasheet99 Table 94. B0h: GVD.VCID – Vendor Capability IDSize: 32 bit Default: 010700