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Register Description
46 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2
2.9.5 MC_SCRUBADDR_HI
This register pair contains part of the address of the last patrol scrub request issued.
When running memtest, the failing address is logged in this register on memtest
errors. Software can write the next address into this register. Scrubbing must be
disabled to reliably read and write this register.
2.10 Integrated Memory Controller RAS Registers
2.10.1 MC_SSRCONTROL
scrubbing control. This register allows the enabling of sparing, patrol scrubbing and
demand scrubbing.
2.10.2 MC_SCRUB_CONTROL
Contains the Scrub control parameters and status.
Device: 3
Function: 0
Offset: 7Ch
Access as a Dword
Bit Type
Reset
Value
Description
12 RO 0 MEMBIST_INPROGRESS. When this bit is asserted by hardware
MemTest/MemInit is in progress.
11 RO 0 MEMBIST_CMPLT. When this bit is asserted by hardware MemTest/MemInit is
complete.
10 WO 0 RESET_MEMBIST_STATUS. When this bit is written to a 1, the status field
MEMBIST_CMPLT is cleared.
9:8 RW 0 CHNL. Can be written to specify the next scrub address with STARTSCRUB in
the MC_SCRUB_CONTROL register. Contains the channel address of the last
patrol scrub issued.
7:6 RW 0 DIMM. Contains the dimm of the last scrub issued. Can be written to specify
the next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register.
5:4 RW 0 RANK. Contains the rank of the last scrub issued. Can be written to specify the
next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register.
3:0 RW 0 BANK. Contains the bank of the last scrub issued. Can be written to specify the
next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register.
Device: 3
Function: 2
Offset: 48h
Access as a Dword
Bit Type
Reset
Value
Description
14:7 RW 0 SCRATCHPAD. This field is available as a scratchpad for Scrubbing operations.
6RW0DEMAND_SCRUB_EN. Enable Demand Scrubs.
1:0 RW 0 SSR_MODE. Spare control enable.
00: Idle
01: Scrub
10: Spare
- Processor 5600 Series 1
- Contents 3
- Revision History 6
- 1 Introduction 7
- Introduction 8
- 2 Register Description 9
- 2.3 Device Mapping 11
- Control Registers 25
- Address Registers 26
- Rank Registers 27
- Thermal Control Registers 28
- 2.5 PCI Standard Registers 36
- 2.6.1 DESIRED_CORES 37
- 2.6.2 MIRROR_PORT_CTL 38
- 2.7.1 SAD_MCSEG_BASE 39
- 2.7.2 SAD_MCSEG_MASK 39
- 2.7.3 SAD_MESEG_BASE 39
- 2.8 Intel QPI Link Registers 40
- 2.8.2 QPI_RMT_QPILP1_STAT_L0 41
- QPI_RMT_QPILP1_STAT_L1 41
- 2.8.3 MIP_PH_CTR_L0 41
- MIP_PH_CTR_L1 41
- 2.8.4 MIP_PH_PRT_L0 42
- MIP_PH_PRT_L1 42
- 2.9.2 MC_SMI__CNTRL 43
- 2.9.3 MC_MAX_DOD 44
- 2.9.4 MC_RD_CRDT_INIT 45
- 2.9.5 MC_SCRUBADDR_HI 46
- 2.10.1 MC_SSRCONTROL 46
- 2.10.2 MC_SCRUB_CONTROL 46
- Registers 47
- MC_CHANNEL_1_RANK_TIMING_A 48
- MC_CHANNEL_2_RANK_TIMING_A 48
- MC_CHANNEL_1_REFRESH_TIMING 50
- MC_CHANNEL_2_REFRESH_TIMING 50
- 2.12 Memory Thermal Control 53
- 2.12.5 MC_DDR_THERM1_STATUS0 55
- MC_DDR_THERM1_STATUS1 55
- MC_DDR_THERM1_STATUS2 55
- Register Description 56
- 56 Intel 56
- 3 Functional Description 57
- RAS Modes 61
- 3.5 Memory Error Signaling 62
- 3.7 2X Refresh 63
- Functional Description 64
- 64 Intel 64
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