Intel BX80619I73970X Scheda Tecnica

Document Number: 326764-004 Desktop 3rd Generation Intel® Core™ Processor Family and Desktop Intel® Pentium® Processor FamilyDatasheet – Volume 1 of 2

Introduction10 Datasheet, Volume 1Figure 1-1. Desktop Processor PlatformIntel®Flexible Display InterfaceDMI2 x4Discrete Graphics (PEG)Analog CRTGigabi

Processor Land and Signal Information100 Datasheet, Volume 1SB_MA[10] AN23 DDR3 OSB_MA[11] AU17 DDR3 OSB_MA[12] AT18 DDR3 OSB_MA[13] AR26 DDR3 OSB_MA[

Datasheet, Volume 1 101Processor Land and Signal Information VCC F18 PWRVCC F19 PWRVCC F21 PWRVCC F22 PWRVCC F24 PWRVCC F25 PWRVCC F27 PWRVCC F28 PWRV

Processor Land and Signal Information102 Datasheet, Volume 1VCCAXG AB36 PWRVCCAXG AB37 PWRVCCAXG AB38 PWRVCCAXG AB39 PWRVCCAXG AB40 PWRVCCAXG AC33 PWR

Datasheet, Volume 1 103Processor Land and Signal Information VCCSA J10 PWRVCCSA K10 PWRVCCSA K11 PWRVCCSA L11 PWRVCCSA L12 PWRVCCSA M10 PWRVCCSA M11 P

Processor Land and Signal Information104 Datasheet, Volume 1VSS AK28 GNDVSS AK31 GNDVSS AK32 GNDVSS AK33 GNDVSS AK34 GNDVSS AK35 GNDVSS AK36 GNDVSS AK

Datasheet, Volume 1 105Processor Land and Signal Information VSS AT28 GNDVSS AT29 GNDVSS AT3 GNDVSS AT30 GNDVSS AT31 GNDVSS AT32 GNDVSS AT33 GNDVSS AT

Processor Land and Signal Information106 Datasheet, Volume 1VSS F10 GNDVSS F13 GNDVSS F14 GNDVSS F17 GNDVSS F2 GNDVSS F20 GNDVSS F23 GNDVSS F26 GNDVSS

Datasheet, Volume 1 107Processor Land and Signal Information § §VSS R39 GNDVSS R8 GNDVSS T1 GNDVSS T5 GNDVSS T6 GNDVSS U8 GNDVSS V1 GNDVSS V2 GNDVSS V

Processor Land and Signal Information108 Datasheet, Volume 1

Datasheet, Volume 1 109DDR Data Swizzling 9 DDR Data SwizzlingTo achieve better memory performance and timing, Intel Design performed DDR Data pin swi

Datasheet, Volume 1 11Introduction 1.1 Processor Feature Details• Four or two execution cores• A 32-KB instruction and 32-KB data first-level cache (L

DDR Data Swizzling110 Datasheet, Volume 1Table 9-1. DDR Data Swizzling Table – Channel ALand Name Land # MC Land NameSA_DQ[0] AJ3 DQ06SA_DQ[1] AJ4 DQ0

DDR Data SwizzlingDatasheet, Volume 1 111§ §Table 9-2. DDR Data Swizzling table – Channel BLand Name Land # MC Land NameSB_DQ[0] AG7 DQ04SB_DQ[1] AG8

DDR Data Swizzling112 Datasheet, Volume 1

Introduction12 Datasheet, Volume 1• Support memory configurations that mix DDR3 DIMMs / DRAMs with DDR3L DIMMs / DRAMs running at 1.5 V• The type of t

Datasheet, Volume 1 13Introduction to transmit data across this interface. This also does not account for packet overhead and link maintenance.• Maxim

Introduction14 Datasheet, Volume 11.2.3 Direct Media Interface (DMI)• DMI 2.0 support• Four lanes in each direction• 5 GT/s point-to-point DMI interfa

Datasheet, Volume 1 15Introduction • DirectX* Video Acceleration (DXVA) support for accelerating video processing— Full AVC/VC1/MPEG2 HW Decode• Advan

Introduction16 Datasheet, Volume 11.3.5 Direct Media Interface (DMI)• L0s and L1 ASPM power management capability1.3.6 Processor Graphics Controller (

Datasheet, Volume 1 17Introduction 1.5 PackageThe processor socket type is noted as LGA 1155. The package is a 37.5 x 37.5 mm Flip Chip Land Grid Arra

Introduction18 Datasheet, Volume 1Notes:1. G2_Core = 2nd Generation Intel® Core™ processor family Desktop, Intel® Pentium® processor Desktop, Intel® C

Datasheet, Volume 1 19Introduction 1.7 TerminologyTable 1-2. Terminology (Sheet 1 of 3)Term DescriptionACPI Advanced Configuration and Power Interfac

2 Datasheet, Volume 1INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERW

Introduction20 Datasheet, Volume 1Intel® VT-dIntel® Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a hardware assist, under sy

Datasheet, Volume 1 21Introduction SVID Serial Voltage IDentification interfaceTAC Thermal Averaging ConstantTAP Test Access PointTCC Thermal Control

Introduction22 Datasheet, Volume 11.8 Related DocumentsNote: Contact your Intel representative for the latest revision of this item.§ §Table 1-3. Rela

Datasheet, Volume 1 23Interfaces 2 InterfacesThis chapter describes the interfaces supported by the processor.2.1 System Memory Interface2.1.1 System

Interfaces24 Datasheet, Volume 1Note:1. DIMM module support is based on availability and is subject to change.Note:1. System memory configurations are

Datasheet, Volume 1 25Interfaces Note:1. System memory timing support is based on availability and is subject to change.2.1.3 System Memory Organizati

Interfaces26 Datasheet, Volume 12.1.3.2.1 Dual-Channel Symmetric ModeDual-Channel Symmetric mode, also known as interleaved mode, provides maximum per

Datasheet, Volume 1 27Interfaces 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)The following sections describe the Just-in-Ti

Interfaces28 Datasheet, Volume 12.2 PCI Express* InterfaceThis section describes the PCI Express interface capabilities of the processor. See the PCI

Datasheet, Volume 1 29Interfaces 2.2.1.1 Transaction LayerThe upper layer of the PCI Express architecture is the Transaction Layer. The Transaction La

Datasheet, Volume 1 3 Contents1Introduction...

Interfaces30 Datasheet, Volume 12.2.2 PCI Express* Configuration MechanismThe PCI Express (external graphics) link is mapped through a PCI-to-PCI brid

Datasheet, Volume 1 31Interfaces 2.2.3 PCI Express* PortThe PCI Express interface on the processor is a single, 16-lane (x16) port that can also be co

Interfaces32 Datasheet, Volume 12.3 Direct Media Interface (DMI)Direct Media Interface (DMI) connects the processor and the PCH. Next generation DMI 2

Datasheet, Volume 1 33Interfaces 2.4 Processor Graphics Controller (GT)New Graphics Engine Architecture includes 3D compute elements, Multi-format har

Interfaces34 Datasheet, Volume 12.4.1.2 3D Pipeline2.4.1.2.1 Vertex Fetch (VF) StageThe VF stage executes 3DPRIMITIVE commands. Some enhancements have

Datasheet, Volume 1 35Interfaces 2.4.1.4 2D EngineThe Display Engine fetches the raw data from the memory, puts the data into a stream, converts the d

Interfaces36 Datasheet, Volume 12.4.2 Processor Graphics DisplayThe Processor Graphics controller display pipe can be broken down into three component

Datasheet, Volume 1 37Interfaces 2.4.2.2 Display PipesThe display pipe blends and synchronizes pixel data received from one or more display planes and

Interfaces38 Datasheet, Volume 12.5 Platform Environment Control Interface (PECI)The PECI is a one-wire interface that provides a communication channe

Datasheet, Volume 1 39Technologies 3 TechnologiesThis chapter provides a high-level description of Intel technologies implemented in the processor.The

4 Datasheet, Volume 12.4.1 3D and Video Engines for Graphics Processing ...332.4.1.1 3D Engine Execution Unit

Technologies40 Datasheet, Volume 13.1.2 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Featu

Datasheet, Volume 1 41Technologies 3.1.4 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) FeaturesThe processor supports th

Technologies42 Datasheet, Volume 13.2 Intel® Trusted Execution Technology (Intel® TXT)Intel Trusted Execution Technology (Intel TXT) defines platform-

Datasheet, Volume 1 43Technologies 3.4 Intel® Turbo Boost TechnologyIntel® Turbo Boost Technology is a feature that allows the processor core to oppor

Technologies44 Datasheet, Volume 13.5 Intel® Advanced Vector Extensions (Intel® AVX)Intel Advanced Vector Extensions (Intel AVX) is the latest expansi

Datasheet, Volume 1 45Technologies 3.6.3 RDRAND InstructionThe processor introduces a software visible random number generation mechanism supported by

Technologies46 Datasheet, Volume 1• More efficient MSR interface to access APIC registers.— To enhance inter-processor and self directed interrupt del

Datasheet, Volume 1 47Power Management 4 Power ManagementThis chapter provides information on the following power management topics:• Advanced Configu

Power Management48 Datasheet, Volume 14.1 Advanced Configuration and Power Interface (ACPI) States SupportedThe ACPI states supported by the processor

Datasheet, Volume 1 49Power Management 4.1.4 PCI Express* Link States4.1.5 Direct Media Interface (DMI) States4.1.6 Processor Graphics Controller Stat

Datasheet, Volume 1 5 4.2.4 Core C-states ... 524.2.4.1 Core C0 S

Power Management50 Datasheet, Volume 14.2 Processor Core Power ManagementWhile executing code, Enhanced Intel SpeedStep Technology optimizes the proce

Datasheet, Volume 1 51Power Management Entry and exit of the C-States at the thread and core level are shown in Figure 4-3.While individual threads ca

Power Management52 Datasheet, Volume 14.2.3 Requesting Low-Power Idle StatesThe primary software interfaces for requesting low power idle states are t

Datasheet, Volume 1 53Power Management 4.2.4.2 Core C1 / C1E StateC1/C1E is a low power state entered when all threads within a core execute a HLT or

Power Management54 Datasheet, Volume 14.2.5 Package C-StatesThe processor supports C0, C1/C1E, C3, and C6 power states. The following is a summary of

Datasheet, Volume 1 55Power Management 4.2.5.1 Package C0Package C0 is the normal operating state for the processor. The processor remains in the norm

Power Management56 Datasheet, Volume 14.2.5.3 Package C3 StateA processor enters the package C3 low power state when:• At least one core is in the C3

Datasheet, Volume 1 57Power Management 4.3.2 DRAM Power Management and InitializationThe processor implements extensive support for power management o

Power Management58 Datasheet, Volume 1It is important to understand that since the power down decision is per rank, the MC can find a lot of opportuni

Datasheet, Volume 1 59Power Management The target behavior is to enter self-refresh for the package C3 and C6 states as long as there are no memory re

6 Datasheet, Volume 17.7 Signal Groups ...807.8 Test A

Power Management60 Datasheet, Volume 14.4 PCI Express* Power Management• Active power management support using L0s and L1 states.• All inputs and outp

Datasheet, Volume 1 61Power Management 4.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)Intel S2DDT reduces display refresh memory traffic by re

Power Management62 Datasheet, Volume 1

Datasheet, Volume 1 63Thermal Management 5 Thermal ManagementFor thermal specifications and design guidelines refer to the Desktop 3rd Generation Inte

Thermal Management64 Datasheet, Volume 1

Datasheet, Volume 1 65Signal Description 6 Signal DescriptionThis chapter describes the processor signals. They are arranged in functional groups acco

Signal Description66 Datasheet, Volume 16.1 System Memory Interface SignalsTable 6-2. Memory Channel A Signals Signal Name Description Direction / Buf

Datasheet, Volume 1 67Signal Description 6.2 Memory Reference and Compensation SignalsTable 6-3. Memory Channel B Signals Signal Name Description Dire

Signal Description68 Datasheet, Volume 16.3 Reset and Miscellaneous SignalsNote:1. PCIe* bifurcation support varies with the processor and PCH SKUs us

Datasheet, Volume 1 69Signal Description 6.4 PCI Express*-based Interface SignalsNote:1. PE_TX[3:0]/PE_TX#[3:0] and PE_RX[3:0]/PE_RX#[3:0] signals are

Datasheet, Volume 1 7 6-2 Memory Channel A Signals ... 666-3 Memory

Signal Description70 Datasheet, Volume 16.6 Direct Media Interface (DMI) Signals6.7 Phase Lock Loop (PLL) Signals6.8 Test Access Points (TAP) SignalsT

Datasheet, Volume 1 71Signal Description 6.9 Error and Thermal Protection SignalsTable 6-11. Error and Thermal Protection Signals Signal Name Descript

Signal Description72 Datasheet, Volume 16.10 Power Sequencing SignalsTable 6-12. Power Sequencing Signals Signal Name Description Direction / Buffer T

Datasheet, Volume 1 73Signal Description 6.11 Processor Power SignalsNote:1. The VCCSA_VID can toggle at most once in 500 uS; The slew rate of VCCSA_V

Signal Description74 Datasheet, Volume 16.13 Ground and Non-Critical to Function (NCTF) Signals6.14 Processor Internal Pull-Up / Pull-Down Resistors§

Datasheet, Volume 1 75Electrical Specifications 7 Electrical Specifications7.1 Power and Ground LandsThe processor has VCC, VDDQ, VCCPLL, VCCSA, VCCAX

Electrical Specifications76 Datasheet, Volume 17.3 Processor Clocking (BCLK[0], BCLK#[0])The processor uses a differential clock to generate the proce

Datasheet, Volume 1 77Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 1 of 3)VID7VID6VID5VID4VID3VID2VID1VID0HE

Electrical Specifications78 Datasheet, Volume 1001011102E0.47500 1 0 1 0 1 1 1 0 A E 1.11500001011112F0.48000 1 0 1 0 1 1 1 1 A F 1.1200000110000300.4

Datasheet, Volume 1 79Electrical Specifications 0 1 0 1 1 1 0 1 5 D 0.71000 1 1 0 1 1 1 0 1 D D 1.350000 1 0 1 1 1 1 0 5 E 0.71500 1 1 0 1 1 1 1 0 D E

8 Datasheet, Volume 1Revision History§ §Revision NumberDescription Revision Date001 • Initial release April 2012002• Added Desktop 3rd Generation Inte

Electrical Specifications80 Datasheet, Volume 17.5 System Agent (SA) VCC VIDThe VCCSA is configured by the processor output land VCCSA_VID. VCCSA_VID

Datasheet, Volume 1 81Electrical Specifications Table 7-2. Signal Groups (Sheet 1 of 2)1Signal Group Type SignalsSystem Reference ClockDifferential CM

Electrical Specifications82 Datasheet, Volume 1Notes:1. Refer to Chapter 8 for signal description details.2. SA and SB refer to DDR3 Channel A and DDR

Datasheet, Volume 1 83Electrical Specifications 7.9 Storage Conditions SpecificationsEnvironmental storage condition limits define the temperature and

Electrical Specifications84 Datasheet, Volume 17.10 DC SpecificationsThe processor DC specifications in this section are defined at the processor pads

Datasheet, Volume 1 85Electrical Specifications Notes:1. Each processor is programmed with a maximum valid voltage identification value (VID), which i

Electrical Specifications86 Datasheet, Volume 1Notes:1. VCCSA must be provided using a separate voltage source and not be connected to VCC. This speci

Datasheet, Volume 1 87Electrical Specifications Notes:1. VAXG is VID based rail.2. The VAXG_MIN and VAXG_MAX loadlines represent static and transient

Electrical Specifications88 Datasheet, Volume 1Notes:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2.

Datasheet, Volume 1 89Electrical Specifications Notes:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2

Datasheet, Volume 1 9Introduction 1 IntroductionThe Desktop 3rd Generation Intel® Core™ processor family and Desktop Intel® Pentium® processor family

Electrical Specifications90 Datasheet, Volume 17.11 Platform Environmental Control Interface (PECI) DC SpecificationsPECI is an Intel proprietary inte

Datasheet, Volume 1 91Electrical Specifications 7.11.2 DC CharacteristicsThe PECI interface operates at a nominal voltage set by VCCIO. The DC electri

Electrical Specifications92 Datasheet, Volume 1

Datasheet, Volume 1 93Processor Land and Signal Information 8 Processor Land and Signal Information8.1 Processor Land AssignmentsThe processor land ma

Processor Land and Signal Information94 Datasheet, Volume 1Figure 8-1. LGA Socket Land Map403938373635343332313029282726252423222120191817161514131211

Datasheet, Volume 1 95Processor Land and Signal Information Table 8-1. Processor Land List by Land NameLand Name Land # Buffer Type Dir.BCLK_ITP C40 D

Processor Land and Signal Information96 Datasheet, Volume 1PECI J35 Async I/OPEG_COMPI B4 Analog IPEG_ICOMPO B5 Analog IPEG_RCOMPO C4 Analog IPEG_RX[0

Datasheet, Volume 1 97Processor Land and Signal Information RSVD D38RSVD H7RSVD H8RSVD J33RSVD J34RSVD J9RSVD K34RSVD K9RSVD L31RSVD L33RSVD L34RSVD L

Processor Land and Signal Information98 Datasheet, Volume 1SA_DQ[44] AR39 DDR3 I/OSA_DQ[45] AR38 DDR3 I/OSA_DQ[46] AN39 DDR3 I/OSA_DQ[47] AN40 DDR3 I/

Datasheet, Volume 1 99Processor Land and Signal Information SB_DQ[6] AJ6 DDR3 I/OSB_DQ[7] AJ7 DDR3 I/OSB_DQ[8] AL7 DDR3 I/OSB_DQ[9] AM7 DDR3 I/OSB_DQ[