Intel BX80623I32100 Scheda Tecnica Pagina 1

Document Number: 324641-0072nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and Intel® Celeron® Process

Introduction10 Datasheet, Volume 1Figure 1-1. Desktop Platform System Block Diagram Example

Processor Pin and Signal Information100 Datasheet, Volume 1VCC C36 PWRVCC D13 PWRVCC D14 PWRVCC D15 PWRVCC D16 PWRVCC D18 PWRVCC D19 PWRVCC D21 PWRVCC

Processor Pin and Signal InformationDatasheet, Volume 1 101VCC J28 PWRVCC J30 PWRVCC K15 PWRVCC K16 PWRVCC K18 PWRVCC K19 PWRVCC K21 PWRVCC K22 PWRVCC

Processor Pin and Signal Information102 Datasheet, Volume 1VCCIO AF8 PWRVCCIO AG33 PWRVCCIO AJ16 PWRVCCIO AJ17 PWRVCCIO AJ26 PWRVCCIO AJ28 PWRVCCIO AJ

Processor Pin and Signal InformationDatasheet, Volume 1 103VSS A35 GNDVSS AA33 GNDVSS AA34 GNDVSS AA35 GNDVSS AA36 GNDVSS AA37 GNDVSS AA38 GNDVSS AA6

Processor Pin and Signal Information104 Datasheet, Volume 1VSS AM30 GNDVSS AM36 GNDVSS AM37 GNDVSS AM38 GNDVSS AM39 GNDVSS AM4 GNDVSS AM40 GNDVSS AM5

Processor Pin and Signal InformationDatasheet, Volume 1 105VSS AV11 GNDVSS AV14 GNDVSS AV17 GNDVSS AV3 GNDVSS AV35 GNDVSS AV38 GNDVSS AV6 GNDVSS AW10

Processor Pin and Signal Information106 Datasheet, Volume 1VSS G34 GNDVSS G7 GNDVSS G8 GNDVSS H1 GNDVSS H17 GNDVSS H2 GNDVSS H20 GNDVSS H23 GNDVSS H26

Processor Pin and Signal InformationDatasheet, Volume 1 107§ §VSS V5 GNDVSS W6 GNDVSS Y5 GNDVSS Y8 GNDVSS_NCTF A4 GNDVSS_NCTF AV39 GNDVSS_NCTF AY37 GN

Processor Pin and Signal Information108 Datasheet, Volume 1

Datasheet, Volume 1 109DDR Data Swizzling9 DDR Data SwizzlingTo achieve better memory performance and better memory timing, Intel design performed the

Datasheet, Volume 1 11Introduction1.1 Processor Feature Details• Four or two execution cores• A 32-KB instruction and 32-KB data first-level cache (L1

DDR Data Swizzling110 Datasheet, Volume 1Table 9-1. DDR Data Swizzling Table – Channel APin Name Pin # MC Pin NameSA_DQ[0] AJ3 DQ01SA_DQ[1] AJ4 DQ02SA

DDR Data SwizzlingDatasheet, Volume 1 111§ §Table 9-2. DDR Data Swizzling Table – Channel BPin Name Pin # MC Pin NameSB_DQ[0] AG7 DQ03SB_DQ[1] AG8 DQ0

DDR Data Swizzling112 Datasheet, Volume 1

Introduction12 Datasheet, Volume 1• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank devices)• Command launch modes of 1n/

Datasheet, Volume 1 13Introduction• 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always

Introduction14 Datasheet, Volume 11.2.4 Platform Environment Control Interface (PECI)The PECI is a one-wire interface that provides a communication ch

Datasheet, Volume 1 15Introduction1.3 Power Management Support1.3.1 Processor Core• Full support of Advanced Configuration and Power Interface (ACPI)

Introduction16 Datasheet, Volume 11.5 Package• The processor socket type is noted as LGA 1155. The package is a 37.5 x 37.5 mm Flip Chip Land Grid Arr

Datasheet, Volume 1 17IntroductionPCHPlatform Controller Hub. The new, 2009 chipset with centralized platform capabilities including the main I/O inte

Introduction18 Datasheet, Volume 11.7 Related DocumentsRefer to Table 1-3 for additional information. § §Table 1-3. Related Documents Document Documen

Datasheet, Volume 1 19Interfaces2 InterfacesThis chapter describes the interfaces supported by the processor. 2.1 System Memory Interface2.1.1 System

2 Datasheet, Volume 1Legal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMP

Interfaces20 Datasheet, Volume 1Note: DIMM module support is based on availability and is subject to change.Notes:1. System memory configurations are

Datasheet, Volume 1 21Interfaces2.1.2 System Memory Timing SupportThe IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command

Interfaces22 Datasheet, Volume 12.1.3.2.1 Dual-Channel Symmetric Mode Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum pe

Datasheet, Volume 1 23Interfaces2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)The following sections describe the Just-in-Tim

Interfaces24 Datasheet, Volume 12.2 PCI Express* InterfaceThis section describes the PCI Express interface capabilities of the processor. See the PCI

Datasheet, Volume 1 25Interfaceshandle packets at those layers. At the receiving side, the reverse process occurs and packets get transformed from the

Interfaces26 Datasheet, Volume 12.2.2 PCI Express* Configuration MechanismThe PCI Express (external graphics) link is mapped through a PCI-to-PCI brid

Datasheet, Volume 1 27Interfaces2.2.4 PCI Express* Lanes ConnectionFigure 2-5 demonstrates the PCIe lanes mapping.2.3 Direct Media Interface (DMI)Dire

Interfaces28 Datasheet, Volume 12.3.3 DMI Link DownThe DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to data link dow

Datasheet, Volume 1 29Interfaces2.4.1 3D and Video Engines for Graphics ProcessingThe 3D graphics pipeline architecture simultaneously operates on dif

Datasheet, Volume 1 3Contents1 Introduction ...

Interfaces30 Datasheet, Volume 12.4.1.2.6 Windower/IZ (WIZ) StageThe WIZ unit performs an early depth test, which removes failing pixels and eliminate

Datasheet, Volume 1 31Interfaces2.4.2 Processor Graphics DisplayThe Processor Graphics controller display pipe can be broken down into three component

Interfaces32 Datasheet, Volume 12.4.2.1.4 Video Graphics Array (VGA)VGA is used for boot, safe mode, legacy games, etc. It can be changed by an applic

Datasheet, Volume 1 33Interfaces2.5 Platform Environment Control Interface (PECI)The PECI is a one-wire interface that provides a communication channe

Interfaces34 Datasheet, Volume 1

Datasheet, Volume 1 35Technologies3 TechnologiesThis chapter provides a high-level description of Intel technologies implemented in the processor.The

Technologies36 Datasheet, Volume 13.1.2 Intel® Virtualization Technology (Intel® VT) forIA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Feature

Datasheet, Volume 1 37Technologies3.1.4 Intel® Virtualization Technology (Intel® VT) for DirectedI/O (Intel® VT-d) FeaturesThe processor supports the

Technologies38 Datasheet, Volume 13.2 Intel® Trusted Execution Technology (Intel® TXT)Intel Trusted Execution Technology (Intel TXT) defines platform-

Datasheet, Volume 1 39Technologies3.4 Intel® Turbo Boost TechnologyIntel® Turbo Boost Technology is a feature that allows the processor core to opport

4 Datasheet, Volume 12.4.1.2 3D Pipeline ... 292.4.1.3 Video Engine ...

Technologies40 Datasheet, Volume 13.5 Intel® Advanced Vector Extensions (Intel® AVX)Intel Advanced Vector Extensions (Intel AVX) is the latest expansi

Datasheet, Volume 1 41Technologies• Provides extensions to scale processor addressability for both the logical and physical destination modes• Adds ne

Technologies42 Datasheet, Volume 1

Datasheet, Volume 1 43Power Management4 Power ManagementThis chapter provides information on the following power management topics: • Advanced Configu

Power Management44 Datasheet, Volume 14.1 Advanced Configuration and Power Interface (ACPI) States SupportedThe ACPI states supported by the processor

Datasheet, Volume 1 45Power Management4.1.5 Direct Media Interface (DMI) States 4.1.6 Processor Graphics Controller States4.1.7 Interface State Combin

Power Management46 Datasheet, Volume 14.2 Processor Core Power ManagementWhile executing code, Enhanced Intel SpeedStep Technology optimizes the proce

Datasheet, Volume 1 47Power ManagementEntry and exit of the C-States at the thread and core level are shown in Figure 4-3.While individual threads can

Power Management48 Datasheet, Volume 14.2.3 Requesting Low-Power Idle StatesThe primary software interfaces for requesting low power idle states are t

Datasheet, Volume 1 49Power Management4.2.4.2 Core C1/C1E StateC1/C1E is a low power state entered when all threads within a core execute a HLT or MWA

Datasheet, Volume 1 54.2.5.1 Package C0 ... 514.2.5.2 Package C1/C1E ...

Power Management50 Datasheet, Volume 14.2.5 Package C-StatesThe processor supports C0, C1/C1E, C3, and C6 power states. The following is a summary of

Datasheet, Volume 1 51Power Management4.2.5.1 Package C0This is the normal operating state for the processor. The processor remains in the normal stat

Power Management52 Datasheet, Volume 14.2.5.3 Package C3 StateA processor enters the package C3 low power state when:• At least one core is in the C3

Datasheet, Volume 1 53Power Management4.3.2 DRAM Power Management and InitializationThe processor implements extensive support for power management on

Power Management54 Datasheet, Volume 1Selection of power modes should be according to power-performance or thermal trade-offs of a given system:• When

Datasheet, Volume 1 55Power Management4.3.2.3 Dynamic Power-down OperationDynamic power-down of memory is employed during normal operation. Based on i

Power Management56 Datasheet, Volume 14.6 Graphics Power Management4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) (also known as CxSR)The In

Datasheet, Volume 1 57Power Management4.6.5 Intel® Graphics Dynamic FrequencyIntel® Graphics Dynamic Frequency Technology is the ability of the proces

Power Management58 Datasheet, Volume 1

Datasheet, Volume 1 59Thermal Management5 Thermal ManagementFor thermal specifications and design guidelines, refer to the 2nd Generation Intel® Core™

6 Datasheet, Volume 17.11.3 Input Device Hysteresis ... 878 Processor Pin and S

Thermal Management60 Datasheet, Volume 1

Datasheet, Volume 1 61Signal Description6 Signal DescriptionThis chapter describes the processor signals. They are arranged in functional groups accor

Signal Description62 Datasheet, Volume 16.1 System Memory Interface SignalsTable 6-2. Memory Channel A Signals Signal Name Description Direction/Buffe

Datasheet, Volume 1 63Signal Description6.2 Memory Reference and Compensation SignalsTable 6-3. Memory Channel B Signals Signal Name Description Direc

Signal Description64 Datasheet, Volume 16.3 Reset and Miscellaneous SignalsNotes:1. PCIe bifurcation support varies with the processor and PCH SKUs us

Datasheet, Volume 1 65Signal Description6.4 PCI Express*-Based Interface SignalsNotes:1. PE_TX[3:0] and PE_RX[3:0] are only used for platforms that su

Signal Description66 Datasheet, Volume 16.6 Direct Media Interface (DMI) Signals6.7 Phase Lock Loop (PLL) Signals6.8 Test Access Points (TAP) SignalsT

Datasheet, Volume 1 67Signal Description6.9 Error and Thermal Protection Signals6.10 Power Sequencing SignalsTable 6-11. Error and Thermal Protection

Signal Description68 Datasheet, Volume 16.11 Processor Power Signals6.12 Sense Signals6.13 Ground and Non-Critical to Function (NCTF) SignalsTable 6-1

Datasheet, Volume 1 69Signal Description6.14 Processor Internal Pull-Up / Pull-Down Resistors§ §Table 6-16. Processor Internal Pull-Up / Pull-Down Res

Datasheet, Volume 1 76-11 Error and Thermal Protection Signals ... 676-12 Power

Signal Description70 Datasheet, Volume 1

Datasheet, Volume 1 71Electrical Specifications7 Electrical Specifications7.1 Power and Ground LandsThe processor has VCC, VDDQ, VCCPLL, VCCSA, VCCAXG

Electrical Specifications72 Datasheet, Volume 17.3 Processor Clocking (BCLK[0], BCLK#[0])The processor uses a differential clock to generate the proce

Datasheet, Volume 1 73Electrical SpecificationsTable 7-1. VR 12.0 Voltage Identification Definition (Sheet 1 of 3)VID7VID6VID5VID4VID3VID2VID1VID0HEX

Electrical Specifications74 Datasheet, Volume 10 0 1 0 1 0 1 1 2 B 0.46000 1 0 101011AB1.100000 0 1 0 1 1 0 0 2 C 0.46500 1 0 101100AC1.105000 0 1 0 1

Datasheet, Volume 1 75Electrical Specifications0 1 0 1 0 1 1 0 5 6 0.67500 1 1 010110D61.315000 1 0 1 0 1 1 1 5 7 0.68000 1 1 010111D71.320000 1 0 1 1

Electrical Specifications76 Datasheet, Volume 17.5 System Agent (SA) VCC VIDThe VCCSA is configured by the processor output pin VCCSA_VID.VCCSA_VID ou

Datasheet, Volume 1 77Electrical Specifications7.7 Signal GroupsSignals are grouped by buffer type and similar characteristics as listed in Table 7-3.

Electrical Specifications78 Datasheet, Volume 1Notes:1. Refer to Chapter 6 and Chapter 8 for signal description details.2. SA and SB refer to DDR3 Cha

Datasheet, Volume 1 79Electrical Specifications7.9 Storage Conditions SpecificationsEnvironmental storage condition limits define the temperature and

8 Datasheet, Volume 1Revision History§ §Revision NumberDescriptionRevision Date001 Initial release January 2011002• Added Intel® Core™ i5-2405S, i5-23

Electrical Specifications80 Datasheet, Volume 17.10 DC SpecificationsThe processor DC specifications in this section are defined at the processor pads

Datasheet, Volume 1 81Electrical SpecificationsNotes:1. Unless otherwise noted, all specifications in this table are based on estimates and simulation

Electrical Specifications82 Datasheet, Volume 1Notes:1. Unless otherwise noted, all specifications in this table are based on estimates and simulation

Datasheet, Volume 1 83Electrical SpecificationsNotes:1. VCCAXG is VID based rail. 2. Unless otherwise noted, all specifications in this table are base

Electrical Specifications84 Datasheet, Volume 1Notes:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2.

Datasheet, Volume 1 85Electrical SpecificationsNotes:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2.

Electrical Specifications86 Datasheet, Volume 17.11 Platform Environmental Control Interface (PECI) DC SpecificationsPECI is an Intel proprietary inte

Datasheet, Volume 1 87Electrical Specifications7.11.2 DC CharacteristicsThe PECI interface operates at a nominal voltage set by VCCIO. The set of DC e

Electrical Specifications88 Datasheet, Volume 1

Datasheet, Volume 1 89Processor Pin and Signal Information8 Processor Pin and Signal Information8.1 Processor Pin AssignmentsThe processor pinmap quad

Datasheet, Volume 1 9Introduction1 IntroductionThe 2nd Generation Intel® Core™ processor family desktop, Intel® Pentium® processor family desktop, and

Processor Pin and Signal Information90 Datasheet, Volume 1Figure 8-1. Socket Pinmap (Top View, Upper-Left Quadrant)

Datasheet, Volume 1 91Processor Pin and Signal InformationFigure 8-2. Socket Pinmap (Top View, Upper-Right Quadrant)

Processor Pin and Signal Information92 Datasheet, Volume 1Figure 8-3. Socket Pinmap (Top View, Lower-Left Quadrant)

Datasheet, Volume 1 93Processor Pin and Signal InformationFigure 8-4. Socket Pinmap (Top View, Lower-Right Quadrant)

Processor Pin and Signal Information94 Datasheet, Volume 1Table 8-1. Processor Pin List by Pin NamePin Name Pin # Buffer Type Dir.BCLK_ITP C40 Diff Cl

Processor Pin and Signal InformationDatasheet, Volume 1 95PE_TX[2] R6 PCI Express OPE_TX[3] U5 PCI Express OPE_TX#[0] P7 PCI Express OPE_TX#[1] T8 PCI

Processor Pin and Signal Information96 Datasheet, Volume 1RSVD AJ30RSVD AJ31RSVD AN20RSVD AP20RSVD AT11RSVD AT14RSVD AU10RSVD AV34RSVD AW34RSVD AY10RS

Processor Pin and Signal InformationDatasheet, Volume 1 97SA_DQ[26] AV9 DDR3 I/OSA_DQ[27] AU9 DDR3 I/OSA_DQ[28] AV7 DDR3 I/OSA_DQ[29] AW7 DDR3 I/OSA_D

Processor Pin and Signal Information98 Datasheet, Volume 1SB_BS[2] AW17 DDR3 OSB_CAS# AK25 DDR3 OSB_CK[0] AL21 DDR3 OSB_CK[1] AL20 DDR3 OSB_CK[2] AL23

Processor Pin and Signal InformationDatasheet, Volume 1 99SB_DQS[6] AL33 DDR3 I/OSB_DQS[7] AG35 DDR3 I/OSB_DQS[8] AN16 DDR3 I/OSB_DQS#[0] AH6 DDR3 I/O