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Datasheet 33

Electrical Specifications

2.7.3 Phase Lock Loop (PLL) and Filter

CCA

and V

CCIOPLL

are power sources required by the PLL clock generators for the Pentium D

processor. Since these PLLs are analog in nature, they require quiet power supplies for minimum

jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core

timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass

filtered from V

The AC low-pass requirements, with input at V

are as follows:

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 2-4.

Table 2-18. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2 BSEL1 BSEL0 FSB Frequency

L L L RESERVED

L L H 133 MHz

L H H RESERVED

L H L 200 MHz

H L L RESERVED

H L H RESERVED

H H H RESERVED

H H L RESERVED

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 105 106

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Intel Pentium D 840 Scheda Tecnica Pagina 33