
10 Datasheet, Volume 1
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Datasheet, Volume 1
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2 Datasheet, Volume 1
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Contents
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4 Datasheet, Volume 1
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Datasheet, Volume 1 5
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6 Datasheet, Volume 1
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Datasheet, Volume 1 7
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8 Datasheet, Volume 1
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Revision History
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10 Datasheet, Volume 1
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1 Introduction
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Introduction
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1.1 Processor Feature Details
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1.2 Interfaces
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1.2.2 PCI Express*
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Datasheet, Volume 1 15
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1.2.5 Processor Graphics
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1.3 Power Management Support
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1.5 Package
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1.6 Terminology
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1.7 Related Documents
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2 Interfaces
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2.1.3.1 Single-Channel Mode
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Flex Memory Technology Mode
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Datasheet, Volume 1 23
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Interfaces
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2.1.5.2 Command Overlap
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2.2 PCI Express* Interface
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2.2.1.1 Transaction Layer
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2.2.1.2 Data Link Layer
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2.2.1.3 Physical Layer
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2.2.3 PCI Express Graphics
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2.3.1 DMI Error Flow
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2.3.3 DMI Link Down
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2.4.1.2 3D Pipeline
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2.4.1.3 Video Engine
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2.4.1.4 2D Engine
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2.4.2.1 Display Planes
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2.4.3 Intel
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2.6 Interface Clocking
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3 Technologies
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Technologies
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Datasheet, Volume 1 37
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3.4 Intel
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Turbo Boost Technology
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3.4.2 Intel
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3.7 Intel
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64 Architecture x2APIC
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4 Power Management
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(ACPI) States Supported
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4.2.1 Enhanced Intel
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SpeedStep
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Technology
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4.2.2 Low-Power Idle States
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Power Management
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4.2.4 Core C-states
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4.2.5 Package C-States
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4.2.5.1 Package C0
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4.2.5.2 Package C1/C1E
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4.2.5.3 Package C3 State
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4.2.5.4 Package C6 State
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Management
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Datasheet, Volume 1 55
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4.6 Graphics Power Management
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4.7 Thermal Power Management
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5 Thermal Management
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5.2.1 Intel
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Reporting
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5.2.2 Package Power Control
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5.2.3 Power Plane Control
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5.2.4 Turbo Time Parameter
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Thermal Management
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Datasheet, Volume 1 69
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5.4.1.3 PROCHOT# Signal
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5.4.2.1 On-Demand Mode
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6 Signal Description
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Signal Description
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Table 6-8. Intel
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6.11 Power Sequencing Signals
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6.12 Processor Power Signals
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6.13 Sense Signals
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7 Electrical Specifications
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7.4 System Agent (SA) V
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7.6 Signal Groups
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Table 7-3. Signal Groups
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(Sheet 2 of 3)
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7.9 DC Specifications
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Table 7-5. Processor Core (V
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±200 mV and the
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Electrical Specifications
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DC Specifications
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8 Processor Pin and Signal
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108 Datasheet, Volume 1
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List by Pin Name
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124 Datasheet, Volume 1
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List by Ball Name
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166 Datasheet, Volume 1
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9 DDR Data Swizzling
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Table – Channel A
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Table – Channel B
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DDR Data Swizzling
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