Intel RH80532GC033512 Scheda Tecnica Pagina 49

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Electrical Specifications
Mobile Intel
Pentium
4 Processor-M Datasheet 49
Figure 23. Stop Grant/Sleep/Deep Sleep Timing
Tt = T70 (Stop Grant Acknowledge Bus Cycle Completion to SLP# Assertion Delay)
Tu = T71 (Input Signals Stable to SLP# assertion requirement)
Tv = T72 (SLP# to DPSLP# assertion)
Tw = T73 (Deep Sleep PLL lock latency)
Tx = T74 (SLP# Hold Time)
Ty = T75 (STPCLK# Hold Time)
Tz = T76 (Input Signal Hold Time)
T
u
stpgnt
BCLK[1:0]
STPCLK#
CPU bus
SLP#
Compatibility
Signals
FrozenChanging
Normal
Stop
Grant
Sleep Deep Sleep Sleep
Stop
Grant
Normal
T
t
T
v
T
y
T
z
T
w
T
x
V0011-02
Changing
DPSLP#
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