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Datasheet, Volume 2 267
Processor Configuration Registers
2.18.4 GCMD_REG—Global Command Register
This register controls remapping hardware. If multiple control fields in this register
need to be modified, software must serialize the modifications through multiple writes
to this register.
0RO 0bUncore
Coherency (C)
This field indicates if hardware access to the root, context, page-
table and interrupt-remap structures are coherent (snooped) or
not.
0 = Hardware accesses to remapping structures are non-
coherent.
1 = Hardware accesses to remapping structures are coherent.
Hardware access to advanced fault log and invalidation queue are
always coherent.
B/D/F/Type: 0/0/0/GFXVTBAR
Address Offset: 10–17h
Reset Value: 0000000000F0101Ah
Access: RO, RO-V
Size: 64 bits
BIOS Optimal Default 00000000000h
Bit Access
Reset
Value
RST/
PWR
Description
B/D/F/Type: 0/0/0/GFXVTBAR
Address Offset: 18–1Bh
Reset Value: 00000000h
Access: RO, WO
Size: 32 bits
BIOS Optimal Default 000000h
Bit Access
Reset
Value
RST/
PWR
Description
31 WO 0b Uncore
Translation Enable (TE)
Software writes to this field to request hardware to
enable/disable DMA-remapping:
0 = Disable DMA remapping
1 = Enable DMA remapping
Hardware reports the status of the translation enable operation
through the TES field in the Global Status register.
There may be active DMA requests in the platform when software
updates this field. Hardware must enable or disable remapping
logic only at deterministic transaction boundaries, so that any in-
flight transaction is either subject to remapping or not at all.
Hardware implementations supporting DMA draining must drain
any in-flight DMA read/write requests queued within the Root-
Complex before completing the translation enable command and
reflecting the status of the command through the TES field in the
Global Status register.
The value returned on a read of this field is undefined.
- Mobile 3rd Generation Intel 1
- Processor Family 1
- Contents 3
- 4 Datasheet, Volume 2 4
- Datasheet, Volume 2 5 5
- 6 Datasheet, Volume 2 6
- Datasheet, Volume 2 7 7
- 8 Datasheet, Volume 2 8
- Datasheet, Volume 2 9 9
- 10 Datasheet, Volume 2 10
- Revision History 11
- 12 Datasheet, Volume 2 12
- 1 Introduction 13
- Introduction 14
- 2 Processor Configuration 15
- 2.2 PCI Devices and Functions 16
- 2.3 System Address Map 17
- 18 Datasheet, Volume 2 18
- 2.3.1 Legacy Address Range 19
- 20 Datasheet, Volume 2 20
- 2.3.1.3 PAM (C_0000h–F_FFFFh) 21
- 22 Datasheet, Volume 2 22
- 2.3.2.2 TSEG 23
- 2.3.2.5 Pre-allocated Memory 24
- 2.3.2.7 Intel 25
- Management Engine (Intel 25
- ME) UMA 25
- 26 Datasheet, Volume 2 26
- 2.3.3.4 High BIOS Area 27
- 28 Datasheet, Volume 2 28
- Datasheet, Volume 2 29 29
- 2.3.4.5 Programming Model 30
- Host/System View 31
- Physical Memory 31
- (DRAM Controller View) 31
- Datasheet, Volume 2 33 33
- 34 Datasheet, Volume 2 34
- Datasheet, Volume 2 35 35
- 36 Datasheet, Volume 2 36
- 2.3.11 I/O Address Space 38
- 2.3.12 MCTP and KVM Flows 39
- 40 Datasheet, Volume 2 40
- Datasheet, Volume 2 41 41
- 42 Datasheet, Volume 2 42
- Datasheet, Volume 2 43 43
- 2.4 I/O Mapped Registers 46
- 2.5.6 CC—Class Code Register 52
- DMA protected range register 59
- 2.5.19 MESEG_BASE—Intel 63
- 2.5.20 MESEG_MASK—Intel 64
- B4h bits 31:20) 80
- 2.6.6 CC—Class Code Register 92
- Register 100
- Port Command Register 112
- 11:10 RW-O 11b Uncore 115
- 5RW-V 0b Uncore 117
- Registers 132
- 104–107h 133
- 108–10Bh 133
- 10C–10Dh 134
- 110–113h 135
- 23 RO 0h Reserved (RSVD) 135
- 114–117h 136
- 11A–11Bh 137
- DA0–DA3h 138
- DA4–DA7h 139
- DA8–DABh 140
- DAC–DAFh 141
- DB0–DB3h 142
- DB4–DB7h 143
- DB8–DBBh 144
- DBC–DBFh 145
- DD8–DDBh 146
- Registers 148
- PCI device 149
- 2.8.6 CC—Class Code Register 152
- Mapped Range Address Register 154
- 2.9 Device 2 IO Registers 160
- 2.10 PCI Device 6 Registers 161
- 2.10.6 CC—Class Code Register 168
- 2RW 0bUncore 180
- of the table in DQWORDS (16 204
- 140–143h 208
- 144–147h 209
- 150–153h 210
- 158–15Bh 210
- 15C–15Fh 211
- 240–243h 211
- 244–247h 212
- C34–C37h 212
- D0C–D0Fh 213
- D34–D37h 213
- D6C–D6Fh 214
- DC0–DC3h 215
- DC4–DC7h 215
- : DCC–DCFh 216
- (DMIBAR) 217
- Declaration Capability 229
- 0 Registers 239
- 4000–4003h 240
- 4028–402Bh 242
- 42A4–42A7h 242
- 4294–4297h 244
- 4298–429Bh 244
- Channel 1 245
- 4404–4407h 247
- 4428–442Bh 247
- 4694–4697h 249
- 4698–469Bh 250
- 46A4–46A7h 250
- 740C–740Fh 251
- 7410–7413h 252
- 5004–5007h 254
- 5008–500Bh 255
- 5060–5063h 256
- Group Registers 257
- 4CB0–4CB3h 258
- 100–107h 290
- 108–10Fh 291
- 200–207h 293
- 208–20Fh 294
- FF0–FF3h 295
- 2.19 PCU MCHBAR Registers 296
- 5880–5883h 297
- 5888–588Bh 298
- Status Report Register 299
- Interrupt Register 300
- 5948–594Bh 301
- 5994–5997h 301
- 5998–599Bh 302
- 5C20–5C23h 302
- 5C24-5C27h 304
- 5D10–5D17h 306
- 2.20 PXPEPBAR Registers 308
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