Datasheet, Volume 2 7

2.13.8 MLT2—Master Latency Timer Register.................................................. 178

2.13.9 HDR2—Header Type Register.............................................................. 178

2.13.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address

2.13.11 GMADR—Graphics Memory Range Address Register ............................... 180

2.13.12 IOBAR—I/O Base Address Register ...................................................... 181

2.13.13 SVID2—Subsystem Vendor Identification Register ................................. 181

2.13.14 SID2—Subsystem Identification Register.............................................. 182

2.13.15 ROMADR—Video BIOS ROM Base Address Register ................................ 182

2.13.16 INTRPIN—Interrupt Pin Register.......................................................... 182

2.13.17 MINGNT—Minimum Grant Register ...................................................... 183

2.13.18 MAXLAT—Maximum Latency Register................................................... 183

2.14 Device 2 I/O Registers..................................................................................... 183

2.14.1 Index—MMIO Address Register ........................................................... 184

2.14.2 Data—MMIO Data Register ................................................................. 184

2.15 DMI and PEG VC0/VCp Remap Registers............................................................. 185

2.15.1 VER_REG—Version Register................................................................ 186

2.15.2 CAP_REG—Capability Register............................................................. 187

2.15.3 ECAP_REG—Extended Capability Register............................................. 190

2.15.4 GCMD_REG—Global Command Register................................................ 191

2.15.5 GSTS_REG—Global Status Register...................................................... 194

2.15.6 RTADDR_REG—Root-Entry Table Address Register................................. 195

2.15.7 CCMD_REG—Context Command Register.............................................. 196

2.15.8 FSTS_REG—Fault Status Register........................................................ 198

2.15.9 FECTL_REG—Fault Event Control Register............................................. 199

2.15.10 FEDATA_REG—Fault Event Data Register.............................................. 200

2.15.11 FEADDR_REG—Fault Event Address Register......................................... 200

2.15.12 FEUADDR_REG—Fault Event Upper Address Register.............................. 200

2.15.13 AFLOG_REG—Advanced Fault Log Register ........................................... 201

2.15.14 PMEM_REG—Protected Memory Enable Register .................................... 202

2.15.15 PLMBASE_REG—Protected Low-Memory Base Register ........................... 203

2.15.16 PLMLIMIT_REG—Protected Low-Memory Limit Register........................... 204

2.15.17 PHMBASE_REG—Protected High-Memory Base Register.......................... 205

2.15.18 PHMLIMIT_REG—Protected High-Memory Limit Register ......................... 206

2.15.19 IQH_REG—Invalidation Queue Head Register ........................................ 206

2.15.20 IQT_REG—Invalidation Queue Tail Register........................................... 207

2.15.21 IQA_REG—Invalidation Queue Address Register .................................... 207

2.15.22 ICS_REG—Invalidation Completion Status Register................................ 208

2.15.23 IECTL_REG—Invalidation Event Control Register.................................... 208

2.15.24 IEDATA_REG—Invalidation Event Data Register..................................... 209

2.15.25 IEADDR_REG—Invalidation Event Address Register................................ 209

2.15.26 IEUADDR_REG—Invalidation Event Upper Address Register..................... 210

2.15.27 IRTA_REG—Interrupt Remapping Table Address Register........................ 210

2.15.28 IVA_REG—Invalidate Address Register................................................. 211

2.15.29 IOTLB_REG—IOTLB Invalidate Register................................................ 212

2.15.30 FRCD_REG—Fault Recording Registers ................................................. 214

2.15.31 VTCMPLRESR—VT Completion Resource Dedication................................ 215

2.15.32 VTFTCHARBCTL—VC0/VCp VTd Fetch Arbiter Control.............................. 216

2.15.33 PEGVTCMPLRESR—PEG VT Completion Resource Dedication.................... 217

2.15.34 VTPOLICY—DMA Remap Engine Policy Control....................................... 219

2.16 DMI VC1 REMAP Registers................................................................................ 221

2.16.1 VER_REG—Version Register................................................................ 222

2.16.2 CAP_REG—Capability Register............................................................. 223

2.16.3 ECAP_REG—Extended Capability Register............................................. 225

2.16.4 GCMD_REG—Global Command Register................................................ 227

2.16.5 GSTS_REG—Global Status Register...................................................... 230

1 2 3 4 5 6 7 8 9 10 11 12 ... 359 360

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