Intel B940 Scheda Tecnica

Document Number: 322910-003Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 SeriesDatasheet – Volume 2J

10 Datasheet, Volume 22.20.5 VC0RCTL—VC0 Resource Control Register...3312.20.6 VC0RSTS—VC0 Resource Status R

Processor Configuration Registers100 Datasheet, Volume 22.8.47 TIS1—Thermal Interrupt Status 1 RegisterThis register is used to report which specific

Datasheet, Volume 2 101Processor Configuration Registers3RW1C 0bAux 3 Thermal Sensor Interrupt Event (A3TSIE)1 = Aux 3 Thermal Sensor trip event occur

Processor Configuration Registers102 Datasheet, Volume 22.8.48 TERATE—Thermometer Mode Enable and Rate RegisterThis common register helps select betwe

Datasheet, Volume 2 103Processor Configuration Registers2.8.49 TERRCMD—Thermal Error Command RegisterThis register select which errors are generate a

Processor Configuration Registers104 Datasheet, Volume 22.8.50 TSMICMD—Thermal SMI Command RegisterThis register selects specific errors to generate a

Datasheet, Volume 2 105Processor Configuration Registers2.8.51 TSCICMD—Thermal SCI Command RegisterThis register selects specific errors to generate a

Processor Configuration Registers106 Datasheet, Volume 22.8.52 TINTRCMD—Thermal INTR Command RegisterThis register selects specific errors to generate

Datasheet, Volume 2 107Processor Configuration Registers2.8.53 EXTTSCS—External Thermal Sensor Control and Status RegisterB/D/F/Type: 0/0/0/MCHBARAddr

Processor Configuration Registers108 Datasheet, Volume 26RW-L 0bThrottling Type Select (TTS)Lockable by EXTTSCS [External Sensor Enable]. If External

Datasheet, Volume 2 109Processor Configuration Registers2.8.54 DDRMPLL1—DDR PLL BIOS RegisterThis register is for DDR PLL register programming.B/D/F/T

Datasheet, Volume 2 11Figures2-1 System Address Range ...182-2 DOS

Processor Configuration Registers110 Datasheet, Volume 22.9 EPBAR Registers2.9.1 EPPVCCAP1—EP Port VC Capability Register 1This register describes the

Datasheet, Volume 2 111Processor Configuration Registers2.9.3 EPVC0RCTL—EP VC 0 Resource Control RegisterThis register controls the resources associat

Processor Configuration Registers112 Datasheet, Volume 22.9.4 EPVC0RCAP—EP VC 0 Resource Capability RegisterB/D/F/Type: 0/0/0/PXPEPBARAddress Offset:

Datasheet, Volume 2 113Processor Configuration Registers2.9.5 EPVC1RCTL—EP VC 1 Resource Control RegisterThis register controls the resources associat

Processor Configuration Registers114 Datasheet, Volume 22.9.6 EPVC1RSTS—EP VC 1 Resource Status RegisterB/D/F/Type: 0/0/0/PXPEPBARAddress Offset: 26–2

Datasheet, Volume 2 115Processor Configuration Registers2.10 PCI Device 1 RegistersTable 2-7. PCI Express* Device 1 Register Address MapAddress Offset

Processor Configuration Registers116 Datasheet, Volume 2A8–A9h DCTL Device Control 0000h RO, RWAA–ABh DSTS Device Status 0000h RO, RW1CAC–AFh LCAP L

Datasheet, Volume 2 117Processor Configuration Registers2.10.1 VID1—Vendor Identification RegisterThis register combined with the Device Identificatio

Processor Configuration Registers118 Datasheet, Volume 28RW 0bSERR# Message Enable (SERRE1)This bit controls Device 1 SERR# messaging. The processor c

Datasheet, Volume 2 119Processor Configuration Registers2.10.4 PCISTS1—PCI Status RegisterThis register reports the occurrence of error conditions ass

12 Datasheet, Volume 2Revision History§Revision NumberDescriptionRevision Date-001 Initial releaseJanuary 2010-002• Added the MCSAMPML—Memory Configur

Processor Configuration Registers120 Datasheet, Volume 22.10.5 RID1—Revision Identification RegisterThis register contains the revision number of the

Datasheet, Volume 2 121Processor Configuration Registers2.10.7 CL1—Cache Line Size Register2.10.8 HDR1—Header Type RegisterThis register identifies th

Processor Configuration Registers122 Datasheet, Volume 22.10.10 SBUSN1—Secondary Bus Number RegisterThis register identifies the bus number assigned t

Datasheet, Volume 2 123Processor Configuration Registers2.10.12 IOBASE1—I/O Base Address RegisterThis register controls the processor to PCI Express-G

Processor Configuration Registers124 Datasheet, Volume 22.10.14 SSTS1—Secondary Status RegisterSSTS1 is a 16-bit status register that reports the occu

Datasheet, Volume 2 125Processor Configuration Registers2.10.15 MBASE1—Memory Base Address RegisterThis register controls the processor to PCI Express

Processor Configuration Registers126 Datasheet, Volume 22.10.16 MLIMIT1—Memory Limit Address RegisterThis register controls the processor to PCI Expre

Datasheet, Volume 2 127Processor Configuration Registers2.10.17 PMBASE1—Prefetchable Memory Base Address RegisterThis register in conjunction with the

Processor Configuration Registers128 Datasheet, Volume 22.10.18 PMLIMIT1—Prefetchable Memory Limit Address RegisterThis register in conjunction with t

Datasheet, Volume 2 129Processor Configuration Registers2.10.20 PMLIMITU1—Prefetchable Memory Limit Address Upper RegisterThe functionality associated

Datasheet, Volume 2 13Introduction1 IntroductionThis is Volume 2 of the Datasheet for the Intel® Core™ i5-600, i3-500 Desktop processor series and Int

Processor Configuration Registers130 Datasheet, Volume 22.10.22 INTRLINE1—Interrupt Line RegisterThis register contains interrupt line routing informa

Datasheet, Volume 2 131Processor Configuration Registers2.10.24 BCTRL1—Bridge Control RegisterThis register provides extensions to the PCICMD1 registe

Processor Configuration Registers132 Datasheet, Volume 22.10.25 MSAC—Multi Size Aperture Control RegisterThis register determines the size of the grap

Datasheet, Volume 2 133Processor Configuration Registers2.10.26 PM_CAPID1—Power Management Capabilities RegisterB/D/F/Type: 0/1/0/PCIAddress Offset: 8

Processor Configuration Registers134 Datasheet, Volume 22.10.27 PM_CS1—Power Management Control/Status RegisterB/D/F/Type: 0/1/0/PCIAddress Offset: 84

Datasheet, Volume 2 135Processor Configuration Registers2.10.28 SS_CAPID—Subsystem ID and Vendor ID Capabilities RegisterThis capability is used to un

Processor Configuration Registers136 Datasheet, Volume 22.10.30 MSI_CAPID—Message Signaled Interrupts Capability ID RegisterWhen a device supports MSI

Datasheet, Volume 2 137Processor Configuration Registers2.10.31 MC—Message Control RegisterSystem software can modify bits in this register, but the d

Processor Configuration Registers138 Datasheet, Volume 22.10.32 MA—Message Address Register2.10.33 MD—Message Data Register2.10.34 PEG_CAPL—PCI Expres

Datasheet, Volume 2 139Processor Configuration Registers2.10.35 PEG_CAP—PCI Express-G Capabilities RegisterThis register indicates PCI Express device

Introduction14 Datasheet, Volume 2

Processor Configuration Registers140 Datasheet, Volume 22.10.37 DCTL—Device Control RegisterThis register provides control for PCI Express device spec

Datasheet, Volume 2 141Processor Configuration Registers2.10.38 DSTS—Device Status RegisterThis register reflects status corresponding to controls in

Processor Configuration Registers142 Datasheet, Volume 22.10.39 LCAP—Link Capabilities RegisterThis register indicates PCI Express device specific cap

Datasheet, Volume 2 143Processor Configuration Registers14:12 RO 100bL0s Exit Latency (L0SELAT)This field indicates the length of time this Port requi

Processor Configuration Registers144 Datasheet, Volume 22.10.40 CTL—Link Control RegisterThis register allows control of PCI Express link.B/D/F/Type:

Datasheet, Volume 2 145Processor Configuration Registers5RW-SC 0bRetrain Link (RL)0 = Normal operation. 1 = Full Link retraining is initiated by direc

Processor Configuration Registers146 Datasheet, Volume 22.10.41 LSTS—Link Status RegisterThis register indicates PCI Express link status.B/D/F/Type: 0

Datasheet, Volume 2 147Processor Configuration Registers9:4 RO 00hNegotiated Link Width (NLW)This field indicates negotiated link width. This field is

Processor Configuration Registers148 Datasheet, Volume 22.10.42 SLOTCAP—Slot Capabilities RegisterNote: Hot Plug is not supported on the platform. B/D

Datasheet, Volume 2 149Processor Configuration Registers2.10.43 SLOTCTL—Slot Control RegisterNote: Hot Plug is not supported on the platform. B/D/F/Ty

Datasheet, Volume 2 15Processor Configuration Registers2 Processor Configuration Registers2.1 Register TerminologyTable 2-1 shows the register-related

Processor Configuration Registers150 Datasheet, Volume 27:6 RO 00bReserved for Attention Indicator Control (AIC)If an Attention Indicator is implement

Datasheet, Volume 2 151Processor Configuration Registers2.10.44 SLOTSTS—Slot Status RegisterNote: Hot Plug is not supported on the platform. B/D/F/Typ

Processor Configuration Registers152 Datasheet, Volume 22RO 0bReserved for MRL Sensor Changed (MSC) If an MRL sensor is implemented, this bit is set w

Datasheet, Volume 2 153Processor Configuration Registers2.10.45 RCTL—Root Control RegisterAllows control of PCI Express Root Complex specific paramete

Processor Configuration Registers154 Datasheet, Volume 22.10.46 RSTS—Root Status RegisterThis register provides information about PCI Express Root Com

Datasheet, Volume 2 155Processor Configuration Registers2.10.48 LSTS2—Link Status 2 Register2.10.49 PEGLC—PCI Express* Legacy Control RegisterThis reg

Processor Configuration Registers156 Datasheet, Volume 22.11 Device 1 Extended Configuration Registers2.11.1 PVCCAP1—Port VC Capability Register 1This

Datasheet, Volume 2 157Processor Configuration Registers2.11.2 PVCCAP2—Port VC Capability Register 2This register describes the configuration of PCI E

Processor Configuration Registers158 Datasheet, Volume 22.11.4 VC0RCAP—VC0 Resource Capability Register2.11.5 VC0RCTL—VC0 Resource Control RegisterThi

Datasheet, Volume 2 159Processor Configuration Registers2.11.6 VC0RSTS—VC0 Resource Status RegisterThis register reports the Virtual Channel specific

Processor Configuration Registers16 Datasheet, Volume 2RW-V-LRead/Write/Volatile/Lockable bit(s). These bits can be read and written by software. Hard

Processor Configuration Registers160 Datasheet, Volume 22.11.7 PEG_TC—PCI Express Completion Timeout RegisterThis register reports PCI Express configu

Datasheet, Volume 2 161Processor Configuration Registers2.12 DMIBAR Registers2.12.1 DMIVCECH—DMI Virtual Channel Enhanced Capability RegisterThis regi

Processor Configuration Registers162 Datasheet, Volume 22.12.2 DMIPVCCAP1—DMI Port VC Capability Register 1Describes the configuration of PCI Express

Datasheet, Volume 2 163Processor Configuration Registers2.12.4 DMIPVCCTL—DMI Port VC Control Register2.12.5 DMIVC0RCAP—DMI VC0 Resource Capability Reg

Processor Configuration Registers164 Datasheet, Volume 22.12.6 DMIVC0RCTL0—DMI VC0 Resource Control RegisterThis register controls the resources assoc

Datasheet, Volume 2 165Processor Configuration Registers2.12.7 DMIVC0RSTS—DMI VC0 Resource Status RegisterThis register reports the Virtual Channel sp

Processor Configuration Registers166 Datasheet, Volume 22.12.9 DMIVC1RCTL1—DMI VC1 Resource Control RegisterThis register controls the resources assoc

Datasheet, Volume 2 167Processor Configuration Registers2.12.10 DMIVC1RSTS—DMI VC1 Resource Status RegisterThis register reports the Virtual Channel s

Processor Configuration Registers168 Datasheet, Volume 22.12.11 DMIVCPRCTL—DMI VCp Resource Control RegisterThis register controls the resources assoc

Datasheet, Volume 2 169Processor Configuration Registers2.12.12 DMIVCPRSTS—DMI VCp Resource Status RegisterThis register reports the Virtual Channel s

Datasheet, Volume 2 17Processor Configuration Registers2.2 System Address MapNote: The processor’s Multi Chip Package (MCP) conceptually consists of t

Processor Configuration Registers170 Datasheet, Volume 22.12.14 DMILE1D—DMI Link Entry 1 Description RegisterThis register provides the first part of

Datasheet, Volume 2 171Processor Configuration Registers2.12.16 DMILE2D—DMI Link Entry 2 Description RegisterThis register provides the first part of

Processor Configuration Registers172 Datasheet, Volume 22.12.18 DMILCAP—DMI Link Capabilities RegisterThis field indicates DMI specific capabilities.B

Datasheet, Volume 2 173Processor Configuration Registers2.12.19 DMILCTL—DMI Link Control RegisterThis register allows control of DMI.2.12.20 DMILSTS—D

Processor Configuration Registers174 Datasheet, Volume 22.13 PCI Device 2, Function 0 Registers2.13.1 VID2—Vendor Identification RegisterThis register

Datasheet, Volume 2 175Processor Configuration Registers2.13.2 DID2—Device Identification RegisterThis register combined with the Vendor Identificatio

Processor Configuration Registers176 Datasheet, Volume 22.13.4 PCISTS2—PCI Status RegisterPCISTS is a 16-bit status register that reports the occurren

Datasheet, Volume 2 177Processor Configuration Registers2.13.5 RID2—Revision Identification RegisterThis register contains the revision number for Dev

Processor Configuration Registers178 Datasheet, Volume 22.13.7 CLS—Cache Line Size RegisterThe IGD does not support this register as a PCI slave.2.13.

Datasheet, Volume 2 179Processor Configuration Registers2.13.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address RegisterThis register

Processor Configuration Registers18 Datasheet, Volume 2Figure 2-1 represents system memory address map in a simplified form. Figure 2-1. System Addres

Processor Configuration Registers180 Datasheet, Volume 22.13.11 GMADR—Graphics Memory Range Address RegisterThe IGD graphics memory base address is sp

Datasheet, Volume 2 181Processor Configuration Registers2.13.12 IOBAR—I/O Base Address RegisterThis register provides the Base offset of the I/O regis

Processor Configuration Registers182 Datasheet, Volume 22.13.14 SID2—Subsystem Identification Register2.13.15 ROMADR—Video BIOS ROM Base Address Regis

Datasheet, Volume 2 183Processor Configuration Registers2.13.17 MINGNT—Minimum Grant Register2.13.18 MAXLAT—Maximum Latency Register2.14 Device 2 I/O

Processor Configuration Registers184 Datasheet, Volume 22.14.1 Index—MMIO Address RegisterA 32 bit I/O write to this port loads the offset of the MMIO

Datasheet, Volume 2 185Processor Configuration Registers2.15 DMI and PEG VC0/VCp Remap RegistersTable 2-11. MMI and PEG VC0/VCp Remap Register Address

Processor Configuration Registers186 Datasheet, Volume 22.15.1 VER_REG—Version RegisterThis register reports the architecture version supported. Backw

Datasheet, Volume 2 187Processor Configuration Registers2.15.2 CAP_REG—Capability RegisterThis register reports general DMA remapping hardware capabil

Processor Configuration Registers188 Datasheet, Volume 223 RO 0bIsochrony (Isoch) 0 = Indicates this DMA-remapping hardware unit has no critical isoch

Datasheet, Volume 2 189Processor Configuration Registers6RO 1bProtected High-Memory Region (PHMR) 0 = Indicates protected high-memory region not suppo

Datasheet, Volume 2 19Processor Configuration Registers2.2.1 Legacy Address RangeThis area is divided into the following address regions:• 0 – 640 KB

Processor Configuration Registers190 Datasheet, Volume 22.15.3 ECAP_REG—Extended Capability RegisterThis register reports DMA-remapping hardware exten

Datasheet, Volume 2 191Processor Configuration Registers2.15.4 GCMD_REG—Global Command RegisterThis register controls DMA-remapping hardware. If multi

Processor Configuration Registers192 Datasheet, Volume 230 WO 0bSet Root Table Pointer (SRTP) Software sets this field to set/update the root-entry ta

Datasheet, Volume 2 193Processor Configuration Registers26 W 0bQueued Invalidation Enable (QIE) This field is valid only for implementations supportin

Processor Configuration Registers194 Datasheet, Volume 22.15.5 GSTS_REG—Global Status RegisterThis register reports general DMA-remapping hardware sta

Datasheet, Volume 2 195Processor Configuration Registers2.15.6 RTADDR_REG—Root-Entry Table Address RegisterThis register provides the base address of

Processor Configuration Registers196 Datasheet, Volume 22.15.7 CCMD_REG—Context Command RegisterRegister to manage context cache. The act of writing t

Datasheet, Volume 2 197Processor Configuration Registers60:59 RO 0hContext Actual Invalidation Granularity (CAIG) Hardware reports the granularity at

Processor Configuration Registers198 Datasheet, Volume 22.15.8 FSTS_REG—Fault Status RegisterThis register indicates the primary fault logging status.

Datasheet, Volume 2 199Processor Configuration Registers2.15.9 FECTL_REG—Fault Event Control RegisterThis register specifies the fault event interrupt

2 Datasheet, Volume 2Legal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IM

Processor Configuration Registers20 Datasheet, Volume 2Non-SMM-mode processor accesses to this range are considered to be to the Video Buffer Area as

Processor Configuration Registers200 Datasheet, Volume 22.15.10 FEDATA_REG—Fault Event Data RegisterThis register specifies the interrupt message data

Datasheet, Volume 2 201Processor Configuration Registers2.15.13 AFLOG_REG—Advanced Fault Log RegisterThis register specifies the base address of memor

Processor Configuration Registers202 Datasheet, Volume 22.15.14 PMEM_REG—Protected Memory Enable RegisterThis register enables the DMA protected memor

Datasheet, Volume 2 203Processor Configuration Registers2.15.15 PLMBASE_REG—Protected Low-Memory Base RegisterThis register is used to setup the base

Processor Configuration Registers204 Datasheet, Volume 22.15.16 PLMLIMIT_REG—Protected Low-Memory Limit RegisterRegister to setup the limit address of

Datasheet, Volume 2 205Processor Configuration Registers2.15.17 PHMBASE_REG—Protected High-Memory Base RegisterThis register is used to setup the base

Processor Configuration Registers206 Datasheet, Volume 22.15.18 PHMLIMIT_REG—Protected High-Memory Limit RegisterRegister to setup the limit address o

Datasheet, Volume 2 207Processor Configuration Registers2.15.20 IQT_REG—Invalidation Queue Tail RegisterRegister indicating the invalidation tail head

Processor Configuration Registers208 Datasheet, Volume 22.15.22 ICS_REG—Invalidation Completion Status RegisterThis register reports the completion st

Datasheet, Volume 2 209Processor Configuration Registers2.15.24 IEDATA_REG—Invalidation Event Data RegisterRegister specifying the Invalidation Event

Datasheet, Volume 2 21Processor Configuration Registers2.2.2 Main Memory Address Range (1MB – TOLUD)This address range extends from 1 MB to the top of

Processor Configuration Registers210 Datasheet, Volume 22.15.26 IEUADDR_REG—Invalidation Event Upper Address RegisterThis register specifies the Inval

Datasheet, Volume 2 211Processor Configuration Registers2.15.28 IVA_REG—Invalidate Address RegisterThis register provides the DMA address whose corres

Processor Configuration Registers212 Datasheet, Volume 22.15.29 IOTLB_REG—IOTLB Invalidate RegisterRegister to control page-table entry caching. The a

Datasheet, Volume 2 213Processor Configuration Registers59:57 RO 0hIOTLB Actual Invalidation Granularity (IAIG) Hardware reports the granularity at wh

Processor Configuration Registers214 Datasheet, Volume 22.15.30 FRCD_REG—Fault Recording RegistersThis registers records DMA-remapping fault informati

Datasheet, Volume 2 215Processor Configuration Registers2.15.31 VTCMPLRESR—VT Completion Resource DedicationThis register provides a programmable inte

Processor Configuration Registers216 Datasheet, Volume 22.15.32 VTFTCHARBCTL—VC0/VCp VTd Fetch Arbiter ControlThis register controls the relative gran

Datasheet, Volume 2 217Processor Configuration Registers2.15.33 PEGVTCMPLRESR—PEG VT Completion Resource DedicationThis register provides a programmab

Processor Configuration Registers218 Datasheet, Volume 214:10 RO 10000bPEG0 VT Completion Tracking Queue Resource Available (PEG0VTCTRA) Number of ent

Datasheet, Volume 2 219Processor Configuration Registers2.15.34 VTPOLICY—DMA Remap Engine Policy ControlThis registers contains all the policy bits re

Processor Configuration Registers22 Datasheet, Volume 22.2.2.2 TSEGThe TSEG register was moved from the GMCH to the processor. The GMCH will have no d

Processor Configuration Registers220 Datasheet, Volume 212 RW-L 0bPEG1 L3 TLBR (PEG1L3TLBR) This is a TLBR policy bit for PEG1VC0 L3 Cache11 RW-L 0bPE

Datasheet, Volume 2 221Processor Configuration Registers2.16 DMI VC1 REMAP RegistersTable 2-12. DMI VC1 Remap Register Address MapAddress OffsetRegist

Processor Configuration Registers222 Datasheet, Volume 22.16.1 VER_REG—Version RegisterThis register reports the architecture version supported. Backw

Datasheet, Volume 2 223Processor Configuration Registers2.16.2 CAP_REG—Capability RegisterThis register reports general DMA remapping hardware capabil

Processor Configuration Registers224 Datasheet, Volume 223 RO 1bIsochrony (Isoch) 0 = Indicates this DMA-remapping hardware unit has no critical isoch

Datasheet, Volume 2 225Processor Configuration Registers2.16.3 ECAP_REG—Extended Capability RegisterThis register reports DMA-remapping hardware exten

Processor Configuration Registers226 Datasheet, Volume 217:8 RO 010hInvalidation Unit Offset (IVO)This field specifies the location to the first IOTLB

Datasheet, Volume 2 227Processor Configuration Registers2.16.4 GCMD_REG—Global Command RegisterThis register controls DMA-remapping hardware. If multi

Processor Configuration Registers228 Datasheet, Volume 228 W 0bEnable Advanced Fault Logging (EAFL) This field is valid only for implementations suppo

Datasheet, Volume 2 229Processor Configuration Registers24 RO 0bSet Interrupt Remap Table Pointer (SIRTP) This field is valid only for implementations

Datasheet, Volume 2 23Processor Configuration RegistersOnce the protected low/high memory region registers are configured, bus master protection to th

Processor Configuration Registers230 Datasheet, Volume 22.16.5 GSTS_REG—Global Status RegisterThis register reports general DMA-remapping hardware sta

Datasheet, Volume 2 231Processor Configuration Registers2.16.6 RTADDR_REG—Root-Entry Table Address RegisterThis register provides the base address of

Processor Configuration Registers232 Datasheet, Volume 22.16.7 CCMD_REG—Context Command RegisterThis register manages context cache. The act of writin

Datasheet, Volume 2 233Processor Configuration Registers60:59 RO 00bContext Actual Invalidation Granularity (CAIG)Hardware reports the granularity at

Processor Configuration Registers234 Datasheet, Volume 22.16.8 FSTS_REG—Fault Status RegisterThis register indicates the various error status.B/D/F/Ty

Datasheet, Volume 2 235Processor Configuration Registers2.16.9 FECTL_REG—Fault Event Control RegisterThis register specifies the fault event interrupt

Processor Configuration Registers236 Datasheet, Volume 22.16.10 FEDATA_REG—Fault Event Data RegisterThis register specifies the interrupt message data

Datasheet, Volume 2 237Processor Configuration Registers2.16.12 FEUADDR_REG—Fault Event Upper Address RegisterThis register specifies the interrupt me

Processor Configuration Registers238 Datasheet, Volume 22.16.14 PMEN_REG—Protected Memory Enable RegisterThis register enables the DMA-protected memor

Datasheet, Volume 2 239Processor Configuration Registers2.16.15 PLMBASE_REG—Protected Low-Memory Base RegisterThis register is used to set up the base

Processor Configuration Registers24 Datasheet, Volume 22.2.2.6.3 Shadow GTT Stolen Space (SGSM)Shadow GSM will be only used once internal GFX and VT-d

Processor Configuration Registers240 Datasheet, Volume 22.16.16 PLMLIMIT_REG—Protected Low-Memory Limit RegisterThis register is used to setup the lim

Datasheet, Volume 2 241Processor Configuration Registers2.16.17 PHMBASE_REG—Protected High-Memory Base RegisterThis register is used to set up the bas

Processor Configuration Registers242 Datasheet, Volume 22.16.18 PHMLIMIT_REG—Protected High-Memory Limit RegisterThis register is used to setup the li

Datasheet, Volume 2 243Processor Configuration Registers2.16.19 IQH_REG—Invalidation Queue Head RegisterThis register indicates the invalidation queue

Processor Configuration Registers244 Datasheet, Volume 22.16.21 IQA_REG—Invalidation Queue Address RegisterThis register is used to configure the base

Datasheet, Volume 2 245Processor Configuration Registers2.16.23 IECTL_REG—Invalidation Event Control RegisterThis register specifies the invalidation

Processor Configuration Registers246 Datasheet, Volume 22.16.24 IEDATA_REG—Invalidation Event Data RegisterThis register specifies the Invalidation Ev

Datasheet, Volume 2 247Processor Configuration Registers2.16.26 IEUADDR_REG—Invalidation Event Upper Address RegisterThis register specifies the Inval

Processor Configuration Registers248 Datasheet, Volume 22.16.28 IVA_REG—Invalidate Address RegisterThis register provides the DMA address whose corres

Datasheet, Volume 2 249Processor Configuration Registers2.16.29 IOTLB_REG—IOTLB Invalidate RegisterThis register is used to invalidate IOTLB. The act

Datasheet, Volume 2 25Processor Configuration RegistersThere are sub-ranges within the PCI Memory address range defined as APIC Configuration Space, M

Processor Configuration Registers250 Datasheet, Volume 259:57 RO 000bIOTLB Actual Invalidation Granularity (IAIG) Hardware reports the granularity at

Datasheet, Volume 2 251Processor Configuration Registers2.16.30 FRCD_REG—Fault Recording RegistersThese Registers record fault information when primar

Processor Configuration Registers252 Datasheet, Volume 22.16.31 VTPOLICY—DMA Remap Engine Policy ControlThis registers contains all the policy bits re

Datasheet, Volume 2 253Processor Configuration Registers2.17 Graphics Control Registers2.17.1 MGGC—Graphics Control RegisterAll the Bits in this regis

Processor Configuration Registers254 Datasheet, Volume 22.17.2 GFXPLL1—GFX PLL BIOSThis is the GFX PLL BIOS register. See latest BIOS specification fo

Datasheet, Volume 2 255Processor Configuration Registers2.18 GFXVTBAR RegistersTable 2-13. GFXVTBAR Register Address MapAddress OffsetRegister SymbolR

Processor Configuration Registers256 Datasheet, Volume 22.18.1 VER_REG—Version RegisterThis register reports the architecture version supported. Backw

Datasheet, Volume 2 257Processor Configuration Registers2.18.2 CAP_REG—Capability RegisterThis register reports general DMA remapping hardware capabil

Processor Configuration Registers258 Datasheet, Volume 223 RO 0bIsochrony (ISOCH) 0 = Indicates this DMA-remapping hardware unit has no critical isoch

Datasheet, Volume 2 259Processor Configuration Registers6RO 1bProtected High-Memory Region (PHMR) 0 = Indicates protected high-memory region is not su

Processor Configuration Registers26 Datasheet, Volume 22.2.2.9 APIC Configuration Space (FEC0_0000h–FECF_FFFFh)This range is reserved for APIC configu

Processor Configuration Registers260 Datasheet, Volume 22.18.3 ECAP_REG—Extended Capability RegisterThis register reports DMA-remapping hardware exten

Datasheet, Volume 2 261Processor Configuration Registers2.18.4 GCMD_REG—Global Command RegisterThis register to controls remapping hardware. If multip

Processor Configuration Registers262 Datasheet, Volume 230 W 0bSet Root Table Pointer (SRTP) Software sets this field to set/update the root-entry tab

Datasheet, Volume 2 263Processor Configuration Registers26 RO 0bQueued Invalidation Enable (QIE) This field is valid only for implementations supporti

Processor Configuration Registers264 Datasheet, Volume 22.18.5 GSTS_REG—Global Status RegisterThis register reports general remapping hardware status.

Datasheet, Volume 2 265Processor Configuration Registers27 RO 0bWrite Buffer Flush Status (WBFS) This field is valid only for implementations requirin

Processor Configuration Registers266 Datasheet, Volume 22.18.6 RTADDR_REG—Root-Entry Table Address RegisterThis register provides the base address of

Datasheet, Volume 2 267Processor Configuration Registers62:61 RW 00bContext Invalidation Request Granularity (CIRG) Software provides the requested in

Processor Configuration Registers268 Datasheet, Volume 22.18.8 FSTS_REG—Fault Status RegisterThis register indicates the various error statuses.B/D/F/

Datasheet, Volume 2 269Processor Configuration Registers1RO-V-S 0bPrimary Pending Fault (PPF) This field indicates if there are one or more pending fa

Datasheet, Volume 2 27Processor Configuration Registers2.2.3 Main Memory Address Space (4 GB to TOUUD)The processor will support 36 bit addressing. Th

Processor Configuration Registers270 Datasheet, Volume 22.18.9 FECTL_REG—Fault Event Control RegisterThis register specifies the fault event interrupt

Datasheet, Volume 2 271Processor Configuration Registers2.18.10 FEDATA_REG—Fault Event Data RegisterThis register specifies the interrupt message data

Processor Configuration Registers272 Datasheet, Volume 22.18.13 AFLOG_REG—Advanced Fault Log RegisterThis register specifies the base address of memor

Datasheet, Volume 2 273Processor Configuration Registers2.18.14 PMEN_REG—Protected Memory Enable RegisterThis register enables the DMA-protected memor

Processor Configuration Registers274 Datasheet, Volume 22.18.15 PLMBASE_REG—Protected Low Memory Base RegisterThis register is used to set up the base

Datasheet, Volume 2 275Processor Configuration Registers2.18.16 PLMLIMIT_REG—Protected Low Memory Limit RegisterThis register is used to set up the li

Processor Configuration Registers276 Datasheet, Volume 22.18.17 PHMBASE_REG—Protected High Memory Base RegisterThis register is used to set up the bas

Datasheet, Volume 2 277Processor Configuration Registers2.18.18 PHMLIMIT_REG—Protected High Memory Limit RegisterThis register is used to set up the l

Processor Configuration Registers278 Datasheet, Volume 22.18.19 IQH_REG—Invalidation Queue Head RegisterThis register indicates the invalidation queue

Datasheet, Volume 2 279Processor Configuration Registers2.18.21 IQA_REG—Invalidation Queue Address RegisterThis register is used to configure the base

Processor Configuration Registers28 Datasheet, Volume 22.2.3.1 Programming ModelThe memory boundaries of interest are:• Bottom of Logical Address Rema

Processor Configuration Registers280 Datasheet, Volume 22.18.23 IECTL_REG—Invalidation Completion Event Control RegisterThis register specifies the in

Datasheet, Volume 2 281Processor Configuration Registers2.18.24 IEDATA_REG—Invalidation Completion Event Data RegisterThis register specifies the Inva

Processor Configuration Registers282 Datasheet, Volume 22.18.26 IRTA_REG—Interrupt Remapping Table Address RegisterThis register provides the base add

Datasheet, Volume 2 283Processor Configuration Registers2.18.27 IVA_REG—Invalidate Address RegisterThis register provides the DMA address whose corres

Processor Configuration Registers284 Datasheet, Volume 22.18.28 IOTLB_REG—IOTLB Invalidate RegisterThis register is used to invalidate IOTLB. The act

Datasheet, Volume 2 285Processor Configuration Registers56:50 RO 00h Reserved 49 RW 0bDrain Reads (DR) This field is ignored by hardware if the DRD f

Processor Configuration Registers286 Datasheet, Volume 22.18.29 FRCD_REG—Fault Recording RegistersRegisters to record fault information when primary f

Datasheet, Volume 2 287Processor Configuration Registers2.18.30 VTPOLICY—VT Policy RegisterB/D/F/Type: 0/2/0/GFXVTBARAddress Offset: FFC–FFFhReset Val

Processor Configuration Registers288 Datasheet, Volume 22.19 PCI Device 6 Registers Note: Device 6 is not supported on all SKUs.Table 2-14. PCI Device

Datasheet, Volume 2 289Processor Configuration Registers2.19.1 VID6—Vendor Identification RegisterThis register, combined with the Device Identificati

Datasheet, Volume 2 29Processor Configuration Registers2.2.3.1.1 Case 1 — Less than 4 GB of Physical Memory (no remap)• Populated Physical Memory = 2

Processor Configuration Registers290 Datasheet, Volume 22.19.2 DID6—Device Identification RegisterThis register combined with the Vendor Identificatio

Datasheet, Volume 2 291Processor Configuration Registers7RO 0bReserved Not Applicable or Implemented. Hardwired to 0. 6RW 0bParity Error Response Ena

Processor Configuration Registers292 Datasheet, Volume 22.19.4 PCISTS6—PCI Status RegisterThis register reports the occurrence of error conditions ass

Datasheet, Volume 2 293Processor Configuration Registers2.19.5 RID6—Revision Identification RegisterThis register contains the revision number of the

Processor Configuration Registers294 Datasheet, Volume 22.19.7 CL6—Cache Line Size Register2.19.8 HDR6—Header Type RegisterThis register identifies th

Datasheet, Volume 2 295Processor Configuration Registers2.19.10 SBUSN6—Secondary Bus Number RegisterThis register identifies the bus number assigned t

Processor Configuration Registers296 Datasheet, Volume 22.19.12 IOBASE6—I/O Base Address RegisterThis register controls the processor to PCI Express-G

Datasheet, Volume 2 297Processor Configuration Registers2.19.14 SSTS6—Secondary Status RegisterSSTS6 is a 16-bit status register that reports the occu

Processor Configuration Registers298 Datasheet, Volume 22.19.15 MBASE6—Memory Base Address RegisterThis register controls the processor to PCI Express

Datasheet, Volume 2 299Processor Configuration Registers2.19.16 MLIMIT6—Memory Limit Address RegisterThis register controls the processor to PCI Expre

Datasheet, Volume 2 3Contents1Introduction...

Processor Configuration Registers30 Datasheet, Volume 22.2.3.1.2 Case 2 — Greater than 4 GB of Physical MemoryNote: Internal graphics is not supported

Processor Configuration Registers300 Datasheet, Volume 22.19.17 PMBASE6—Prefetchable Memory Base Address RegisterThis register in conjunction with the

Datasheet, Volume 2 301Processor Configuration Registers2.19.18 PMLIMIT6—Prefetchable Memory Limit Address RegisterThis register in conjunction with t

Processor Configuration Registers302 Datasheet, Volume 22.19.19 PMBASEU6—Prefetchable Memory Base Address Upper RegisterThe functionality associated w

Datasheet, Volume 2 303Processor Configuration Registers2.19.20 PMLIMITU6—Prefetchable Memory Limit Address Upper RegisterThe functionality associated

Processor Configuration Registers304 Datasheet, Volume 22.19.22 INTRLINE6—Interrupt Line RegisterThis register contains interrupt line routing informa

Datasheet, Volume 2 305Processor Configuration Registers9RO 0bSecondary Discard Timer (SDT) Not Applicable or Implemented. Hardwired to 0. 8RO 0bPrima

Processor Configuration Registers306 Datasheet, Volume 22.19.25 PM_CAPID6—Power Management Capabilities RegisterB/D/F/Type: 0/6/0/PCIAddress Offset: 8

Datasheet, Volume 2 307Processor Configuration Registers2.19.26 PM_CS6—Power Management Control/Status RegisterB/D/F/Type: 0/6/0/PCIAddress Offset: 84

Processor Configuration Registers308 Datasheet, Volume 22.19.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities RegisterThis capability is used to un

Datasheet, Volume 2 309Processor Configuration Registers2.19.29 MSI_CAPID—Message Signaled Interrupts Capability ID RegisterWhen a device supports MSI

Datasheet, Volume 2 31Processor Configuration Registers2.2.3.1.3 Case 3 — 4 GB or less of Physical MemoryNote: Internal graphics is not supported on t

Processor Configuration Registers310 Datasheet, Volume 22.19.30 MC—Message Control RegisterSystem software can modify bits in this register, but the d

Datasheet, Volume 2 311Processor Configuration Registers2.19.31 MA—Message Address Register2.19.32 MD—Message Data Register2.19.33 PEG_CAPL—PCI Expres

Processor Configuration Registers312 Datasheet, Volume 22.19.34 PEG_CAP—PCI Express-G Capabilities RegisterThis register indicates PCI Express device

Datasheet, Volume 2 313Processor Configuration Registers2.19.36 DCTL—Device Control RegisterThis register provides control for PCI Express device spec

Processor Configuration Registers314 Datasheet, Volume 22.19.37 DSTS—Device Status RegisterThis register reflects status corresponding to controls in

Datasheet, Volume 2 315Processor Configuration Registers2.19.38 LCAP—Link Capabilities RegisterThis register indicates PCI Express device specific cap

Processor Configuration Registers316 Datasheet, Volume 214:12 RO 100bL0s Exit Latency (L0SELAT) This field indicates the length of time this Port requ

Datasheet, Volume 2 317Processor Configuration Registers2.19.39 LCTL—Link Control RegisterThis register allows control of PCI Express link.B/D/F/Type:

Processor Configuration Registers318 Datasheet, Volume 25RW-SC 0bRetrain Link (RL) 0 = Normal operation. 1 = Full Link retraining is initiated by dire

Datasheet, Volume 2 319Processor Configuration Registers2.19.40 LSTS—Link Status RegisterThis register indicates PCI Express link status.B/D/F/Type: 0

Processor Configuration Registers32 Datasheet, Volume 22.2.3.1.4 Case 4 — Greater than 4 GB of Physical Memory, RemapNote: Internal graphics is not su

Processor Configuration Registers320 Datasheet, Volume 22.19.41 SLOTCAP—Slot Capabilities RegisterNote: Hot Plug is not supported on the platform. 3:0

Datasheet, Volume 2 321Processor Configuration Registers5RO 0bReserved for Hot-plug Surprise (HPS) When set to 1, this bit indicates that an adapter p

Processor Configuration Registers322 Datasheet, Volume 22.19.42 SLOTCTL—Slot Control RegisterNote: Hot Plug is not supported on the platforms. B/D/F/T

Datasheet, Volume 2 323Processor Configuration Registers7:6 RO 00bReserved for Attention Indicator Control (AIC) If an Attention Indicator is implemen

Processor Configuration Registers324 Datasheet, Volume 22.19.43 SLOTSTS—Slot Status RegisterNote: Hot Plug is not supported on the platform. B/D/F/Typ

Datasheet, Volume 2 325Processor Configuration Registers2RO 0bReserved for MRL Sensor Changed (MSC) If an MRL sensor is implemented, this bit is set w

Processor Configuration Registers326 Datasheet, Volume 22.19.44 RCTL—Root Control RegisterThis register allows control of PCI Express Root Complex spe

Datasheet, Volume 2 327Processor Configuration Registers2.19.45 RSTS—Root StatusThis register provides information about PCI Express Root Complex spec

Processor Configuration Registers328 Datasheet, Volume 22.20 Device 6 Extended Configuration Registers Note: Device 6 is not supported on all SKUs.2.2

Datasheet, Volume 2 329Processor Configuration Registers2.20.2 PVCCAP2—Port VC Capability Register 2This register describes the configuration of PCI E

Datasheet, Volume 2 33Processor Configuration Registers2.2.4 PCI Express* Configuration Address SpacePCIEXBAR has moved to the processor. The processo

Processor Configuration Registers330 Datasheet, Volume 22.20.4 VC0RCAP—VC0 Resource Capability RegisterB/D/F/Type: 0/6/0/MMRAddress Offset: 110–113hRe

Datasheet, Volume 2 331Processor Configuration Registers2.20.5 VC0RCTL—VC0 Resource Control RegisterThis register controls the resources associated wi

Processor Configuration Registers332 Datasheet, Volume 22.20.6 VC0RSTS—VC0 Resource Status Register2.21 Intel® Trusted Execution Technology (Intel® TX

Datasheet, Volume 2 333Processor Configuration Registers2.21.1 TXT.DID—TXT Device ID RegisterThis register contains the TXT ID for the processor.2.21.

Processor Configuration Registers334 Datasheet, Volume 22.21.3 TXT.PUBLIC.KEY.LOWER—TXT Processor Public Key HashLower Half RegisterThese registers ho

Datasheet, Volume 2 335Intel® QuickPath Architecture System Address Decode Register Description3 Intel® QuickPath Architecture System Address Decode R

Intel® QuickPath Architecture System Address Decode Register Description336 Datasheet, Volume 2RWORead/Write Once. A register bit with this attribute

Datasheet, Volume 2 337Intel® QuickPath Architecture System Address Decode Register Description3.2 Platform Configuration StructureThe processor conta

Intel® QuickPath Architecture System Address Decode Register Description338 Datasheet, Volume 23.3 Detailed Configuration Space MapsTable 3-3. Device

Datasheet, Volume 2 339Intel® QuickPath Architecture System Address Decode Register DescriptionTable 3-4. Device 0, Function 1 — System Address Decode

Processor Configuration Registers34 Datasheet, Volume 22.2.6 Graphics Memory Address RangesThe processor can be programmed to direct memory accesses t

Intel® QuickPath Architecture System Address Decode Register Description340 Datasheet, Volume 2Table 3-5. Device 2, Function 0 — Intel® QPI Link 0 Reg

Datasheet, Volume 2 341Intel® QuickPath Architecture System Address Decode Register DescriptionTable 3-6. Device 2, Function 1 — Intel® QPI Physical 0

Intel® QuickPath Architecture System Address Decode Register Description342 Datasheet, Volume 23.4 PCI Standard RegistersThese registers appear in eve

Datasheet, Volume 2 343Intel® QuickPath Architecture System Address Decode Register Description3.4.3 RID—Revision Identification RegisterThis register

Intel® QuickPath Architecture System Address Decode Register Description344 Datasheet, Volume 23.4.4 CCR—Class Code RegisterThis register contains the

Datasheet, Volume 2 345Intel® QuickPath Architecture System Address Decode Register Description3.4.5 HDR—Header Type RegisterThis register identifies

Intel® QuickPath Architecture System Address Decode Register Description346 Datasheet, Volume 23.4.7 PCICMD—Command RegisterThis register defines the

Datasheet, Volume 2 347Intel® QuickPath Architecture System Address Decode Register Description3.4.8 PCISTS—PCI Status RegisterThe PCI Status register

Intel® QuickPath Architecture System Address Decode Register Description348 Datasheet, Volume 24RO0Capability List (CLIST)This bit is hard wired to 1

Datasheet, Volume 2 349Intel® QuickPath Architecture System Address Decode Register Description3.5 Generic Non-core Registers3.5.1 MAX_RTIDSMaximum nu

Datasheet, Volume 2 35Processor Configuration Registers2.2.7 System Management Mode (SMM)The processor handles all SMM mode transaction routing. The p

Intel® QuickPath Architecture System Address Decode Register Description350 Datasheet, Volume 225:24 RW 0PAM3_LOENABLE. 0D0000h–0D3FFFh Attribute (LOE

Datasheet, Volume 2 351Intel® QuickPath Architecture System Address Decode Register Description3.6.2 SAD_PAM456This register is for legacy Device 0, F

Intel® QuickPath Architecture System Address Decode Register Description352 Datasheet, Volume 23.6.3 SAD_HENThis register is for legacy Hole Enable.De

Datasheet, Volume 2 353Intel® QuickPath Architecture System Address Decode Register Description3.6.4 SAD_SMRAMThis register is for legacy 9Dh address

Intel® QuickPath Architecture System Address Decode Register Description354 Datasheet, Volume 23.6.5 SAD_PCIEXBARThis is the Global register for PCIEX

Datasheet, Volume 2 355Intel® QuickPath Architecture System Address Decode Register Description3.6.6 SAD_DRAM_RULE_0, SAD_DRAM_RULE_1, SAD_DRAM_RULE_2

Intel® QuickPath Architecture System Address Decode Register Description356 Datasheet, Volume 23.7 Intel® QPI Link Registers3.7.1 QPI_QPILCL_L0, QPI_Q

Datasheet, Volume 2 357Intel® QuickPath Architecture System Address Decode Register Description3.8 Intel® QPI Physical Layer Registers3.8.1 QPI_0_PH_C

Intel® QuickPath Architecture System Address Decode Register Description358 Datasheet, Volume 23.8.2 QPI_0_PH_CTR, QPI_1_PH_CTRThis is the Intel QPI P

Datasheet, Volume 2 359Intel® QuickPath Architecture System Address Decode Register Description3.8.3 QPI_0_PH_PIS, QPI_1_PH_PISThis is an Intel QPI Ph

Processor Configuration Registers36 Datasheet, Volume 2locations can be accessed only during I/O address wrap-around when address bit 16 is asserted.

Intel® QuickPath Architecture System Address Decode Register Description360 Datasheet, Volume 2

Datasheet, Volume 2 37Processor Configuration RegistersNote that the processor Device 1 I/O address range registers defined above are used for all I/O

Processor Configuration Registers38 Datasheet, Volume 22.4 Configuration MechanismsThe GMCH is the originator of configuration cycles. Internal to the

Datasheet, Volume 2 39Processor Configuration Registers2.4.2 PCI Express* Enhanced Configuration MechanismPCI Express extends the configuration space

4 Datasheet, Volume 22.7.12 MCHBAR—MCH Memory Mapped Register Range Base Register...522.7.13 GGC—Graphics Control Register ...

Processor Configuration Registers40 Datasheet, Volume 2Just the same as with PCI devices, each device is selected based on decoded address information

Datasheet, Volume 2 41Processor Configuration Registers2.4.4 Internal Device Configuration AccessesThe processor decodes the Bus Number (Bits 23:16) a

Processor Configuration Registers42 Datasheet, Volume 22.4.5 Bridge Related Configuration AccessesConfiguration accesses on PCI Express or DMI are PCI

Datasheet, Volume 2 43Processor Configuration Registers2.4.5.2 DMI Configuration AccessesAccesses to disabled processor internal devices, bus numbers

Processor Configuration Registers44 Datasheet, Volume 2positions must first be read, merged with the new values for other bit positions and then writt

Datasheet, Volume 2 45Processor Configuration Registers2.7 PCI Express* Device 0 RegistersTable 2-4 shows the PCI Express Device 0 register address ma

Processor Configuration Registers46 Datasheet, Volume 22.7.1 VID—Vendor Identification RegisterThis register combined with the Device Identification r

Datasheet, Volume 2 47Processor Configuration Registers2.7.3 PCICMD—PCI Command RegisterSince processor Device 0 does not physically reside on PCI_A m

Processor Configuration Registers48 Datasheet, Volume 22.7.4 PCISTS—PCI Status RegisterThis status register reports the occurrence of error events on

Datasheet, Volume 2 49Processor Configuration Registers2.7.5 RID—Revision IdentificationThis register contains the revision number of the processor. T

Datasheet, Volume 2 52.8.37 SSKPD—Sticky Scratchpad Data Register ...942.8.38 TSC1—Thermal Sensor Control

Processor Configuration Registers50 Datasheet, Volume 22.7.8 HDR—Header Type RegisterThis register identifies the header layout of the configuration s

Datasheet, Volume 2 51Processor Configuration Registers2.7.10 SID—Subsystem Identification RegisterThis value is used to identify a particular subsyst

Processor Configuration Registers52 Datasheet, Volume 22.7.12 MCHBAR—MCH Memory Mapped Register Range Base RegisterThis is the base address for the pr

Datasheet, Volume 2 53Processor Configuration Registers2.7.13 GGC—Graphics Control RegisterAll the bits in this register are Intel TXT lockable.B/D/F/

Processor Configuration Registers54 Datasheet, Volume 22.7.14 DEVEN—Device Enable RegisterThis register allows for enabling/disabling of PCI devices a

Datasheet, Volume 2 55Processor Configuration Registers2.7.15 DMIBAR—Root Complex Register Range Base Address RegisterThis is the base address for the

Processor Configuration Registers56 Datasheet, Volume 22.7.16 LAC—Legacy Access Control RegisterThis 8-bit register controls steering of MDA cycles.Th

Datasheet, Volume 2 57Processor Configuration Registers0RW 0bPEG0 MDA Present (MDAP0)This bit works with the VGA Enable bits in the BCTRL register of

Processor Configuration Registers58 Datasheet, Volume 22.7.17 TOUUD—Top of Upper Usable DRAM RegisterThis 16 bit register defines the Top of Upper Usa

Datasheet, Volume 2 59Processor Configuration Registers2.7.19 BGSM—Base of GTT Pre-allocated Memory RegisterThis register contains the base address o

6 Datasheet, Volume 22.10.31 MC—Message Control Register...1372.10.32 MA—Message Address Reg

Processor Configuration Registers60 Datasheet, Volume 22.7.21 TOLUD—Top of Low Usable DRAM RegisterThis 16-bit register defines the Top of Low Usable

Datasheet, Volume 2 61Processor Configuration Registers2.7.22 PBFC—Primary Buffer Flush Control Register2.7.23 SBFC—Secondary Buffer Flush Control Reg

Processor Configuration Registers62 Datasheet, Volume 22.7.24 ERRSTS—Error Status RegisterThis register is used to report various error conditions usi

Datasheet, Volume 2 63Processor Configuration Registers2.7.25 ERRCMD—Error Command RegisterThis register controls the processor responses to various s

Processor Configuration Registers64 Datasheet, Volume 22.7.26 SMICMD—SMI Command RegisterThis register enables various errors to generate an SMI DMI s

Datasheet, Volume 2 65Processor Configuration Registers2.7.28 CAPID0—Capability Identifier RegisterThis register is used to report various processor c

Processor Configuration Registers66 Datasheet, Volume 22.8 MCHBAR RegistersTable 2-5. MCHBAR Register Address Map (Sheet 1 of 2)Address OffsetRegister

Datasheet, Volume 2 67Processor Configuration Registers1001–1002h TSC1Thermal Sensor Control 10000h RW-L, RO, RW, AF1004–1005h TSS1 Thermal Sensor Sta

Processor Configuration Registers68 Datasheet, Volume 22.8.1 CSZMAP—Channel Size Mapping RegisterThis register indicates the total memory that is mapp

Datasheet, Volume 2 69Processor Configuration Registers2.8.2 CHDECMISC—Channel Decode Miscellaneous RegisterThis register provides enhanced addressing

Datasheet, Volume 2 72.13.8 MLT2—Master Latency Timer Register... 1782.13.9 HDR2—Header Type Register..

Processor Configuration Registers70 Datasheet, Volume 22.8.3 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 RegisterThe DRAM Rank Boundary Registers de

Datasheet, Volume 2 71Processor Configuration Registers2.8.4 C0DRB1—Channel 0 DRAM Rank Boundary Address 1 RegisterSee C0DRB0 register description for

Processor Configuration Registers72 Datasheet, Volume 22.8.6 C0DRB3—Channel 0 DRAM Rank Boundary Address 3 RegisterSee C0DRB0 register description for

Datasheet, Volume 2 73Processor Configuration Registers2.8.7 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute RegisterThe DRAM Rank Attribute Registers defin

Processor Configuration Registers74 Datasheet, Volume 22.8.8 C0DRA23—Channel 0 DRAM Rank 2,3 Attribute RegisterSee C0DRA01 register description for pr

Datasheet, Volume 2 75Processor Configuration Registers2.8.10 C0CYCTRKPCHG—Channel 0 CYCTRK PCHG RegisterB/D/F/Type: 0/0/0/MCHBARAddress Offset: 250-2

Processor Configuration Registers76 Datasheet, Volume 22.8.11 C0CYCTRKACT—Channel 0 CYCTRK ACT RegisterB/D/F/Type: 0/0/0/MCHBARAddress Offset: 252–255

Datasheet, Volume 2 77Processor Configuration Registers2.8.12 C0CYCTRKWR—Channel 0 CYCTRK WR Register2.8.13 C0CYCTRKRD—Channel 0 CYCTRK READ RegisterB

Processor Configuration Registers78 Datasheet, Volume 22.8.14 C0CYCTRKREFR—Channel 0 CYCTRK REFR RegisterThis register provides Channel 0 CYCTRK Refre

Datasheet, Volume 2 79Processor Configuration Registers2.8.16 C0REFRCTRL—Channel 0 DRAM Refresh Control RegisterThis register provides settings to con

8 Datasheet, Volume 22.16.6 RTADDR_REG—Root-Entry Table Address Register ...2312.16.7 CCMD_REG—Context Command Register

Processor Configuration Registers80 Datasheet, Volume 221:20 RW 00bDRAM Refresh Hysterisis (REFHYSTERISIS)Hysterisis level — useful for dref_high wate

Datasheet, Volume 2 81Processor Configuration Registers2.8.17 C0JEDEC—Channel 0 JEDEC Control RegisterThis is the Channel 0 JEDEC Control Register.B/D

Processor Configuration Registers82 Datasheet, Volume 22.8.18 C0ODT—Channel 0 ODT Matrix RegisterThis is an ODT related configuration register. It is

Datasheet, Volume 2 83Processor Configuration Registers9RW 0bDODTRD0R1 (sd0_cr_rdrank0_r1odt)Assert rank1 ODT during Reads from RANK0.1 = ON0 = OFF8RW

Processor Configuration Registers84 Datasheet, Volume 22.8.19 C0ODTCTRL—Channel 0 ODT Control Register2.8.20 C0DTC—Channel 0 DRAM Throttling Control R

Datasheet, Volume 2 85Processor Configuration Registers2.8.21 C0RSTCTL—Channel 0 Reset Controls RegisterThis register contains all the reset controls

Processor Configuration Registers86 Datasheet, Volume 22.8.22 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 RegisterThe operation of this register is

Datasheet, Volume 2 87Processor Configuration Registers2.8.25 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 RegisterThe operation of this register is

Processor Configuration Registers88 Datasheet, Volume 22.8.28 C1WRDATACTRL—Channel 1 Write Data Control RegisterThis register provides Channel 1 Write

Datasheet, Volume 2 89Processor Configuration Registers2.8.30 C1CYCTRKACT—Channel 1 CYCTRK ACT RegisterThis register provides Channel 1 CYCTRK ACT con

Datasheet, Volume 2 92.18.27 IVA_REG—Invalidate Address Register... 2832.18.28 IOTLB_REG—IOTLB Invalidat

Processor Configuration Registers90 Datasheet, Volume 22.8.31 C1CYCTRKWR—Channel 1 CYCTRK WR RegisterThis register provides Channel 1 CYCTRK WR contro

Datasheet, Volume 2 91Processor Configuration Registers2.8.33 C1CKECTRL—Channel 1 CKE Control RegisterThis register provides Channel 1 CKE Control.B/D

Processor Configuration Registers92 Datasheet, Volume 22.8.34 C1PWLRCTRL—Channel 1 Partial Write Line Read Control RegisterThis register is to configu

Datasheet, Volume 2 93Processor Configuration Registers2.8.36 C1DTC—Channel 1 DRAM Throttling Control RegisterProgrammable Event weights are input int

Processor Configuration Registers94 Datasheet, Volume 22.8.37 SSKPD—Sticky Scratchpad Data RegisterThis register holds 64 writable bits with no functi

Datasheet, Volume 2 95Processor Configuration Registers2.8.39 TSS1—Thermal Sensor Status 1 RegisterThis read only register provides trip point and oth

Processor Configuration Registers96 Datasheet, Volume 22.8.41 TOF1—Thermometer Offset 1 RegisterThis register is used for programming the thermometer

Datasheet, Volume 2 97Processor Configuration Registers2.8.43 TSTTPA1—Thermal Sensor Temperature Trip Point A1 RegisterThis register sets the target v

Processor Configuration Registers98 Datasheet, Volume 22.8.44 TSTTPB1—Thermal Sensor Temperature Trip Point B1 RegisterThis register sets the target v

Datasheet, Volume 2 99Processor Configuration Registers2.8.46 HWTHROTCTRL1—Hardware Throttle Control 1 RegisterB/D/F/Type: 0/0/0/MCHBARAddress Offset: