
Summary Tables of Changes
Specification Update 39
Performance Monitoring Event FP_ASSIST May Not Be Accurate
CPL-Qualified BTS May Report Incorrect Branch-From Instruction
Address
PEBS Does Not Always Differentiate Between CPL-Qualified
Events
PMI May Be Delayed to Next PEBS Event
PEBS Buffer Overflow Status Will Not Be Indicated Unless
IA32_DEBUGCTL[12] Is Set
The BS Flag in DR6 May Be Set for Non-Single-Step #DB
Exception
An Asynchronous MCE during a Far Transfer May Corrupt ESP
B0-B3 Bits in DR6 May Not Be Properly Cleared after Code
Breakpoint
BTM/BTS Branch-From Instruction Address May Be Incorrect for
Software Interrupts
REP Store Instructions in a Specific Situation May Cause the
Processor to Hang
Performance Monitor SSE Retired Instructions May Return
Incorrect Values
Performance Monitoring Events for L1 and L2 Miss May Not Be
Accurate
A MOV Instruction from CR8 Register with 16 Bit Operand Size Will
Leave Bits 63:16 of the Destination Register Unmodified
Debug Register May Contain Incorrect Information on a MOVSS or
POPSS Instruction followed by SYSRET
Single Step Interrupts with Floating Point Exception Pending May
Be Mishandled
Fault on ENTER Instruction May Result in Unexpected Values on
Stack Frame
Unaligned Accesses to Paging Structures May Cause the
Processor to Hang
INVLPG Operation for Large (2M/4M) Pages May Be Incomplete
under Certain Conditions
Page Access Bit May Be Set Prior to Signaling a Code Segment
Limit Fault
Update of Attribute Bits on Page Directories without Immediate
TLB Shootdown May Cause Unexpected Processor Behavior
Invalid Instructions May Lead to Unexpected Behavior
EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after
Shutdown
Commenti su questo manuale