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Datasheet, Volume 2 203

Processor Configuration Registers

2.12.21 LSTS—DMI Link Status Register

This register indicates DMI status.

B/D/F/Type: 0/0/0/DMIBAR

Address Offset: 8A–8Bh

Reset Value: 0001h

Access: RO-V

Size: 16 bits

BIOS Optimal Default 00h

Bit Attr

Reset

Value

RST/

PWR

Description

15:12 RO 0h Reserved

11 RO-V 0b Uncore

Link Training (TXTRN)

When set, this bit indicates that the Physical Layer TXTSSM is in

the Configuration or Recovery state, or that 1b was written to the

Retrain Link bit but Link training has not yet begun.

Hardware clears this bit when the TXTSSM exits the

Configuration/Recovery state once Link training is complete.

10 RO 0h Reserved

9:4 RO-V 00h Uncore

Negotiated Width (NWID)

This field indicates negotiated link width. This field is valid only

when the link is in the L0, L0s, or L1 states (after link width

negotiation is successfully completed).

00h = Reserved

01h = X1

02h = X2

04h = X4

All other encodings are reserved.

3:0 RO-V 1h Uncore

Negotiated Speed (NSPD)

This field indicates negotiated link speed.

1h = 2.5 Gb/s

2h = 5.0 Gb/s

All other encodings are reserved.

The value in this field is undefined when the Link is not up.

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Intel E3-1275 Scheda Tecnica Pagina 203