Intel 386 Manuale Utente Scaricare il pdf (Pagina 150)

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6-37

BUS INTERFACE UNIT

• NMI pin - The request is recognized and latched. It is serviced after HOLD is released.

• SMI# pin - The request is recognized and latched. It is serviced after HOLD is released.

6.5.2 HOLD Signal Latency

Because other bus masters may be used in time-critical applications, the amount of time the bus

master must wait for bus access (HOLD latency) can be a critical design consideration. Because

a bus cycle must be terminated before HLDA can go active, the maximum possible latency occurs

when a bus-cycle instruction is being executed or a DMA block mode transfer is in progress. Wait

states increase latency, and HOLD is not recognized between locked bus cycles and interrupt ac-

knowledge cycles. The internal DMA may also contribute to the latency.

The HOLD latency is dependent on a number of parameters:

• The instruction being executed at the time the HOLD request occurs.

• The number of wait states during various access cycles, including the following:

— Memory wait states

— Code fetch wait states

— Interrupt acknowledge wait states

— Refresh wait states

• The priority of the requester.

• The mode of the DMA:

— Block mode

— Single cycle mode

— Demand transfer mode

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Intel 386 Manuale Utente Pagina 150

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