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100

101

4-7

SYSTEM REGISTER ORGANIZATION

Figure 4-3. Address Configuration Register (REMAPCFG)

Address Configuration Register

REMAPCFG

Expanded Addr:

PC/AT Address:

Reset State:

0022H

0000H

15 8

ESE——— ————

7 0

— S1R S0R ISR IMR DR — TR

Bit

Number

Bit

Mnemonic

Function

15 ESE 0 = Disables expanded I/O space

1 = Enables expanded I/O space

14–7 — Reserved.

6 S1R 0 = Makes serial channel 1 (COM2) accessible in both DOS I/O space

and expanded I/O space

1 = Remaps serial channel 1 (COM2) address into expanded I/O space

5 S0R 0 = Makes serial channel 0 (COM1) accessible in both DOS I/O space

and expanded I/O space

1 = Remaps serial channel 0 (COM1) address into expanded I/O space

4 ISR 0 = Makes the slave 82C59A interrupt controller accessible in both DOS

I/O space and expanded I/O space

1 = Remaps slave 82C59A interrupt controller address into expanded

I/O space

3 IMR 0 = Makes the master 82C59A interrupt controller accessible in both

DOS I/O space and expanded I/O space

1 = Remaps master 82C59A interrupt controller address into expanded

I/O space

2 DR 0 = Makes the DMA address accessible in both DOS I/O space and

expanded I/O space

1 = Remaps DMA address into expanded I/O space

1 — Reserved.

0 TR 0 = Makes the timer control unit accessible in both DOS I/O space and

expanded I/O space

1 = Remaps timer control unit address into expanded I/O space

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 690 691

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Intel 386 Manuale Utente Pagina 58

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