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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

D-28

D.23 ICW1 (MASTER AND SLAVE)

Initialization Command Word 1

ICW1 (master and slave)

(write only)

Expanded Addr:

ISA Addr:

Reset State:

master slave

F020H F0A0H

0020H 00A0H

XXH XXH

7 0

0 0 0 RSEL1 LS 0 0 1

Bit

Number

Bit

Mnemonic

Function

7–5 — Clear these bits to guarantee device operation.

4 RSEL1 Register Select 1 (Also see OCW2 and OCW3):

ICW1, OCW2, and OCW3 are accessed through the same addresses.

0 = OCW2 or OCW3 is accessed (Figure 9-13 and Figure 9-15).

1 = ICW1 register is accessed.

3 LS Level/Edge Sensitive:

0 = Selects edge-triggered IR input signals.

1 = Selects level-sensitive IR input signals.

All internal peripherals interface with the 82C59As in edge-triggered

mode only. This is compatible with the PC/AT bus specification. Each

source signal initiates an interrupt request by making a low-to-high

transition. External peripherals interface with the 8259As in edge-

triggered or level-sensitive mode. The modes are selected for the

device, not for individual interrupts.

NOTE: If an internal peripheral interrupt is used, the 8259A that the

interrupt is connected to must be programmed for edge-triggered

interrupts.

2–1 — Clear these bits to guarantee device operation.

0 — Set this bit to guarantee device operation.

NOTE: The 82C59A must be initialized before it can be used. After reset, the 82C59A register states are

undefined. The 82C59A modules must be initialized before the IF flag in the core FLAG register is

set. All peripherals that use interrupts connected to the ICU must be initialized before initializing

the ICU.

1 2 ... 588 589 590 591 592 593 594 595 596 597 598 ... 690 691

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Intel 386 Manuale Utente Pagina 593

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