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Appendix C: BMC Sensor Tables Intel® Workstation Board S5520SC TPS
Revision 1.7
Intel order number: E39530-010
154
Full Sensor Name
(Sensor name in SDR)
Sensor #
Platform
Applicability
Sensor Type
Event/Readin
g Type
Event Offset
Triggers
Contrib. To
System
Status
Assert/D
e-assert
Readable
Value/Off
sets
Event
Data
Rearm
Stand-
by
SMI Timeout
(SMI Timeout)
06h All
SMI Timeout
F3h
Digital
Discrete
03h
01 – State
asserted
Fatal
As and
De
– Trig Offset
A –
System Event Log
(System Event Log)
07h All
Event Logging
Disabled
10h
Sensor
Specific
6Fh
02 - Log area
reset/cleared
OK As – Trig Offset
A X
System Event
(System Event)
08h All
System Event
12h
Sensor
Specific
6Fh
04 – PEF action OK As - Trig Offset
A,I X
BB +1.1V IOH
(BB +1.1V IOH)
10h All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
As and
De
Analog R, T A –
BB +1.1V P1 Vccp
(BB +1.1V P1 Vccp)
11h All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
As and
De
Analog R, T A –
BB +1.1V P2 Vccp
(BB +1.1V P2 Vccp)
12h All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
As and
De
Analog R, T A –
BB +1.5V P1 DDR3
(BB +1.5V P1 DDR3)
13h All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
As and
De
Analog R, T A –
BB +1.5V P2 DDR3
(BB +1.5V P2 DDR3)
14h All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
As and
De
Analog R, T A –
BB +1.8V AUX
(BB +1.8V AUX)
15h All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
As and
De
Analog R, T A X
- Workstation Board S5520SC 1
- Revision History 2
- Disclaimers 3
- Table of Contents 4
- List of Figures 9
- Revision 1.7 10
- List of Tables 11
- 1. Introduction 15
- 2. Overview 16
- Overview 19
- 3. Functional Architecture 30
- 3.1 Intel 31
- 5520 I/O Hub (IOH) 31
- 3.2 Processor Support 32
- 3.2.3 Intel 34
- Technology (EIST) 34
- 3.3 Memory Subsystem 36
- 3.3.2 Supported Memory 38
- 3.3.5 Memory Interleaving 42
- 3.3.6 Memory Test 43
- 3.3.7 Memory Scrub Engine 43
- 3.3.8 Memory RAS 43
- Tables 5 and 6 47
- 3.4 ICH10R 49
- Revision 1.7 50
- 3.5 PCI Subsystem 52
- 3.6 Intel 53
- 3.6.1 SAS RAID Support 54
- 3.8 Serial Ports 57
- 3.9 Floppy Disk Controller 58
- 3.11 Video Support 58
- 3.11.1 Video Modes 59
- 3.11.2 Dual Video 59
- 3.13 Audio Codec 62
- 3.14 IEEE 1394a Support 63
- 3.15.1 Overview 64
- 3.15.2 TPM security BIOS 64
- 3.16 ACPI Support 67
- 3.17 Intel 67
- Virtualization Technology 67
- 4. Platform Management 68
- 4.2.3 Media Redirection 71
- 4.2.5 Embedded Web server 73
- 4.3 Platform Control 74
- 4.3.2 Fan Speed Control 75
- 4.4 Intel 78
- 5. BIOS Setup Utility 80
- 5.3.1 Operation 81
- 5.3.2.1 Main Screen 84
- 5.3.2.2.1 Processor Screen 87
- 5.3.2.2.2 Memory Screen 90
- 5.3.2.2.6 PCI Screen 98
- Revision 1.7 103
- 5.3.2.6 Boot Options Screen 108
- 6.2 Power Connectors 119
- 6.3.1 Intel 121
- RMM3) Connector 121
- 6.3.2 LCP/IPMB Header 121
- 6.4 Front Panel Connector 122
- 6.5 I/O Connectors 123
- 6.5.3 SAS Module Slot 124
- 6.5.5 USB Connector 125
- 6.5.6 IEEE 1394a connectors 127
- 6.6 Audio Connectors 128
- 6.7 Onboard Video Header 128
- 6.8 Fan Headers 129
- 7. Jumper Blocks 131
- 7.1.1 Clearing the CMOS 132
- 7.1.2 Clearing the Password 132
- 7.3 BIOS Recovery 133
- 8. Intel 135
- Light Guided Diagnostics 135
- 8.2 Fan Fault LEDs 136
- A. System Status LED 137
- B. System ID LED 137
- 8.4 DIMM Fault LEDs 139
- 9.1 Intel 141
- 9.2 MTBF 141
- Table 76. MTBF Estimate 142
- Revision 1.7 144
- 9.4.1 Grounding 145
- 9.4.2 Stand-by Outputs 146
- 9.4.3 Remote Sense 146
- 9.4.4 Voltage Regulation 146
- 9.4.5 Dynamic Loading 147
- 9.4.6 Capacitive Loading 147
- 9.4.7 Ripple/Noise 147
- 9.4.8 Timing Requirements 148
- Table 84. Turn On/Off Timing 149
- FCC (USA) 153
- ICES-003 (Canada) 155
- VCCI (Japan) 155
- BSMI (Taiwan) 155
- RRL KCC (Korea) 156
- 10.7 CA Perchlorate Warning 159
- Appendix B: Compatible Intel 162
- Server Chassis 162
- POST Error Beep Codes 185
- Glossary 188
- Reference Documents 192
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