Intel S5520SC Specifiche Pagina 32

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Functional Architecture Intel® Workstation Board S5520SC TPS
Revision 1.7
Intel order number: E39530-010
18
3.1.3 Enterprise South Bridge Interface (ESI)
One x4 ESI link interface that supports the PCI Express* Gen1 (2.5 Gbps) transfer rate for
connecting Intel
®
ICH10R in the Intel
®
Workstation Board S5520SC.
3.1.4 Manageability Engine (ME)
An embedded ARC controller is within the IOH providing the Intel
®
Server Platform Services
(SPS). The controller is also commonly referred to as the Manageability Engine (ME).
3.1.5 Controller Link (CL)
The Controller Link is a private, low-pin count (LPC), low power, communication interface
between the IOH and the ICH10 portions of the Manageability Engine subsystem.
3.2 Processor Support
The Intel
®
Workstation Board S5520SC supports the following processors:
z One or two Intel
®
Xeon
®
Processor 5500 Series with a 4.8 GT/s, 5.86 GT/s, or 6.4
GT/s Intel
®
QPI link interface and Thermal Design Power (TDP) up to 130 W.
z One or two Intel
®
Xeon
®
Processor 5600 Series with a 6.4 GT/s Intel
®
QPI link
interface and Thermal Design Power (TDP) up to 130 W.
z Supports Intel
®
Xeon
®
Processor 5500 Series and Intel
®
Xeon
®
Processor 5600
Series processor(s) with maximum 130 W power in the Intel
®
Server Chassis
SC5650WS
z Supports Intel
®
Xeon
®
Processor 5500 Series processor(s) with maximum 95 W
power in the Intel
®
Server Chassis SC5600Base
z Supports Intel
®
Xeon
®
Processor 5600 Series processor(s) with maximum 130 W
power in the Intel
®
Server Chassis SC5600Base
The server boards do not support previous generations of the Intel
®
Xeon
®
processors.
For a complete, updated list of supported processors, see:
http://support.intel.com/support/motherboards/server/S5520SC/
. On the Support tab, look for
Compatibility and then Supported Processor List.
3.2.1 Processor Population Rules
You must populate processors in sequential order. Therefore, you must populate processor
socket 1 (CPU 1) before processor socket 2 (CPU 2).
When only one processor is installed, it must be in the socket labeled CPU1, which is located
near the rear edge of the server board. When a single processor is installed, no terminator is
required in the second processor socket.
For optimum performance, when two processors are installed, both must be the identical
revision and have the same core voltage and Intel
®
QPI/core speed.
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