
Revision History Intel® Workstation Board S5520SC TPS
Revision 1.7
Intel order number: E39530-010
ii
Revision History
Date Revision
Number
Modifications
February 2008 0.1 Preliminary draft
April 2008 0.5 Content update
April 2008 0.55 Content update
September 2008 0.6 Memory upgrade rule updated; product code updated; and added pin-out of internal
video header
February 2009 1.0 Updated Functional Architecture Section; updated Regulatory and Certification
Information; and added Platform Specific Appendix.
March 2009 1.1
– Updated Section 3.3.4.1 Memory Reservation for Memory-mapped Functions
– Updated Section 3.4.1.2 onboard SATA Storage Mode Matrix table
– Added Fan Domain Table in Section 4.3.2.2.1
– Updated Section 9.2 MTBF
– Added Appendix G Installation Guidelines
– Added Processor Stepping Mismatching on Table 2
– Updated Boot Option BIOS Setup Menu (Table 35 and Figure 34)
– Updated Table 4 Memory Running Frequency
– Updated Table 9 Intel® SAS Entry RAID Module AXX4SASMOD Storage Mode
– Updated Table 14 Graphics Card Population
– Updated Table 48 and Table 49, CPU 1 and CPU2 power connectors pin-out
– Updated Table 89 POST Codes and Messages
– Updated Table 92 BMC Beep Codes
– Updated Figure 19 SMBUS Block Diagram, revised components code name
– Updated Figure 53 Power Distribution Block Diagram, revised components code
name
July 2009 1.2
– Updated Section 2.1, Section 3.1.8, Section 3.3.2, Section 3.3.3, Section 3.11.3,
Section 3.18, and Section 4.2.2
– Updated Table 2, Table 8, Table 26, and Table 29
– Updated Figure 3 and Figure 13
August 2009 1.3
– Updated Section 7.3
– Updated Section 6.8 and Table 46: corrected connector silkscreen numeration
November 2009 1.4
– Updated Section 3.3.3
– Updated Section 3.3.9
– Updated Section 3.13
March 2010 1.5
– Updated Section 2.1, added Intel® Xeon® Processor 5600 series support
– Updated Section 3.2, added Intel® Xeon® Processor 5600 series support
April 2010 1.6
– Removed CCC related notice
May 2010 1.7
– Updated Section 3.3.2 for memory capacity
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